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Logic Decomposition of SpeedIndependent Circuits
 PROCEEDINGS OF THE IEEE
, 1999
"... ... This paper presents a new method for logic decomposition of speedindependent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches ..."
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Cited by 7 (1 self)
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... This paper presents a new method for logic decomposition of speedindependent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous
Symbolic Model Checking without BDDs
, 1999
"... Symbolic Model Checking [3, 14] has proven to be a powerful technique for the verification of reactive systems. BDDs [2] have traditionally been used as a symbolic representation of the system. In this paper we show how boolean decision procedures, like Stalmarck's Method [16] or the Davis ..."
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Cited by 910 (74 self)
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& Putnam Procedure [7], can replace BDDs. This new technique avoids the space blow up of BDDs, generates counterexamples much faster, and sometimes speeds up the verification. In addition, it produces counterexamples of minimal length. We introduce a bounded model checking procedure for LTL
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
Verification of SpeedIndependent DataPath
 In IEE ProceedingsComputers and Digital Techniques
, 1996
"... This paper demonstrates that verification techniques developed for relatively large, synchronous circuits can be applied to speedindependent, selftimed circuits. We introduce local formulas which provide a natural way to specify the input/output behaviour of datapath circuits. The validity of ..."
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of a local formula is independent of the order in which the operations occur in a speedindependent circuit. We demonstrate our approach with the verification of two designs: a FIFO, and a vector multiplier chip.
Symbolic Model Checking: 10^20 States and Beyond
, 1992
"... Many different methods have been devised for automatically verifying finite state systems by examining stategraph models of system behavior. These methods all depend on decision procedures that explicitly represent the state space using a list or a table that grows in proportion to the number of st ..."
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Cited by 753 (40 self)
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to symbolic model checking by discussing how it can be used to verify a simple synchronous pipeline circuit.
Symbolic Model Checking for Realtime Systems
 INFORMATION AND COMPUTATION
, 1992
"... We describe finitestate programs over realnumbered time in a guardedcommand language with realvalued clocks or, equivalently, as finite automata with realvalued clocks. Model checking answers the question which states of a realtime program satisfy a branchingtime specification (given in an ..."
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Cited by 574 (50 self)
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We describe finitestate programs over realnumbered time in a guardedcommand language with realvalued clocks or, equivalently, as finite automata with realvalued clocks. Model checking answers the question which states of a realtime program satisfy a branchingtime specification (given
Structural Methods for the Synthesis of SpeedIndependent Circuits
, 1996
"... Most existing tools for the synthesis of asynchronouscircuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based on the structural analysis of the underlying Petri net. This methodology can be ..."
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Cited by 20 (10 self)
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Most existing tools for the synthesis of asynchronouscircuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based on the structural analysis of the underlying Petri net. This methodology can be applied to any STG that can be covered by State Machines and, in particular, to all live and safe freechoice STGs. Significant improvements with regard to existing structural methods are provided. The new techniques have been implemented in an experimental tool that has been able to synthesize specificationswith over10 27 markings, some of them being nonfree choice. 1 Introduction Petri nets (PNs) are a powerful formalism to model concurrent systems. As a model, their most interesting feature is the capability of implicitly describing a vast state space by a succinct representation, which gracefully captures the notions of causality, concurrency and conflict between events. Petri nets...
Covering Conditions and Algorithms for the Synthesis of SpeedIndependent Circuits
 IEEE Transactions on ComputerAided Design
, 1998
"... This paper presents theory and algorithms for the synthesis of standard Cimplementations of speedindependent circuits. These implementations are blocklevel circuits which may consist of atomic gates to perform complex functions in order to ensure hazardfreedom. First, we present boolean covering ..."
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Cited by 14 (5 self)
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This paper presents theory and algorithms for the synthesis of standard Cimplementations of speedindependent circuits. These implementations are blocklevel circuits which may consist of atomic gates to perform complex functions in order to ensure hazardfreedom. First, we present boolean covering
Hierarchical GateLevel Verification of SpeedIndependent Circuits
 In Asynchronous Design Methodologies
, 1995
"... This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite ..."
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Cited by 6 (3 self)
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This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite
Synthesis of Speedindependent circuits from STGunfolding segment
 Proc. 34th ACM/IEEE Design Automation Conference
, 1997
"... This paper presents a novel technique for synthesis of speedindependent circuits. It is based on partial order representation of the state graph called STGunfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic implem ..."
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Cited by 4 (1 self)
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This paper presents a novel technique for synthesis of speedindependent circuits. It is based on partial order representation of the state graph called STGunfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic
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