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Cacheoblivious shortest paths in graphs using buffer heap
 IN PROCEEDINGS OF THE 16TH ACM SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES
, 2004
"... We present the Buffer Heap (BH), a cacheoblivious priority queue that supports DeleteMin, Delete, and DecreaseKey operations in O ( 1 B log2 N) amortized block transfers from B external memory, where B is the (unknown) blocksize and N is the maximum number of elements in the queue. As is common ..."
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Cited by 9 (3 self)
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in the same amortized bound. The amortized time bound for each operation is O(log N). We also present a CacheOblivious Tournament Tree (COTT), which is simpler than the Buffer Heap, but has weaker bounds. Using the Buffer Heap we present cacheoblivious algorithms for undirected and directed single
Cacheoblivious shortest paths in graphs . . .
 SPAA'04
, 2004
"... We present the Buffer Heap (BH), a cacheoblivious priority queue that supports DeleteMin, Delete, and DecreaseKey operations in O( 1 ..."
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We present the Buffer Heap (BH), a cacheoblivious priority queue that supports DeleteMin, Delete, and DecreaseKey operations in O( 1
Cacheoblivious planar shortest paths
 In Proc. 32nd International Colloquium on Automata, Languages, and Programming. LNCS
, 2005
"... Abstract. We present an efficient cacheoblivious implementation of the shortestpath algorithm for planar graphs by Klein et al., and prove that it incurs no more than O ` N B1/2−ɛ + N B log N ´ block transfers on a graph with N vertices. This is the first cacheoblivious algorithm for this problem ..."
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Cited by 1 (1 self)
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Abstract. We present an efficient cacheoblivious implementation of the shortestpath algorithm for planar graphs by Klein et al., and prove that it incurs no more than O ` N B1/2−ɛ + N B log N ´ block transfers on a graph with N vertices. This is the first cacheoblivious algorithm
Cacheoblivious priority queue and graph algorithm applications
 In Proc. 34th Annual ACM Symposium on Theory of Computing
, 2002
"... In this paper we develop an optimal cacheoblivious priority queue data structure, supporting insertion, deletion, and deletemin operations in O ( 1 B logM/B N) amortized memory B transfers, where M and B are the memory and block transfer sizes of any two consecutive levels of a multilevel memory hi ..."
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Cited by 68 (9 self)
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critical component in many of the best known externalmemory graph algorithms, and using our cacheoblivious priority queue we develop several cacheoblivious graph algorithms.
Cacheoblivious algorithms and data structures
 IN SWAT
, 2004
"... Frigo, Leiserson, Prokop and Ramachandran in 1999 introduced the idealcache model as a formal model of computation for developing algorithms in environments with multiple levels of caching, and coined the terminology of cacheoblivious algorithms. Cacheoblivious algorithms are described as stand ..."
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Cited by 11 (1 self)
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Frigo, Leiserson, Prokop and Ramachandran in 1999 introduced the idealcache model as a formal model of computation for developing algorithms in environments with multiple levels of caching, and coined the terminology of cacheoblivious algorithms. Cacheoblivious algorithms are described
Fibonacci Heaps and Their Uses in Improved Network . . .
, 1987
"... In this paper we develop a new data structure for implementing heaps (priority queues). Our structure, Fibonacci heaps (abbreviated Fheaps), extends the binomial queues proposed by Vuillemin and studied further by Brown. Fheaps support arbitrary deletion from an nitem heap in qlogn) amortized t ..."
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Cited by 746 (18 self)
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in the problem graph: ( 1) O(n log n + m) for the singlesource shortest path problem with nonnegative edge lengths, improved from O(m logfmh+2)n); (2) O(n*log n + nm) for the allpairs shortest path problem, improved from O(nm lo&,,,+2,n); (3) O(n*logn + nm) for the assignment problem (weighted bipartite
Cacheoblivious data structures
, 2005
"... The memory system of most modern computers consists of a hierarchy of memory levels, with each level acting as a cache for the next; for a typical desktop computer the hierarchy consists of registers, level 1 cache, level 2 cache, level 3 cache, main memory, and disk. One of the essential characteri ..."
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Cited by 18 (5 self)
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The memory system of most modern computers consists of a hierarchy of memory levels, with each level acting as a cache for the next; for a typical desktop computer the hierarchy consists of registers, level 1 cache, level 2 cache, level 3 cache, main memory, and disk. One of the essential
CacheOblivious Algorithms and Data Structures
"... 1 Introduction Modern computers are characterized by having a memory system consisting ofa hierarchy of several levels of memory, where each level is acting as a cache for the next level [46]. The typical memory levels of current machines are registers,level 1 cache, level 2 cache, level 3 cache, ma ..."
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1 Introduction Modern computers are characterized by having a memory system consisting ofa hierarchy of several levels of memory, where each level is acting as a cache for the next level [46]. The typical memory levels of current machines are registers,level 1 cache, level 2 cache, level 3 cache
Results 1  10
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37,424