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System architecture directions for networked sensors

by Jason Hill, Robert Szewczyk, Alec Woo, Seth Hollar, David Culler, Kristofer Pister - IN ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS , 2000
"... Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the physical world or spread throughout our environment. The missing elements are an overall system architecture and a methodo ..."
Abstract - Cited by 1789 (58 self) - Add to MetaCart
Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the physical world or spread throughout our environment. The missing elements are an overall system architecture and a

A Scalable, Commodity Data Center Network Architecture

by Mohammad Al-Fares, Alexander Loukissas, Amin Vahdat , 2008
"... Today’s data centers may contain tens of thousands of computers with significant aggregate bandwidth requirements. The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. Unfo ..."
Abstract - Cited by 466 (18 self) - Add to MetaCart
Today’s data centers may contain tens of thousands of computers with significant aggregate bandwidth requirements. The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy

Modeling the effect of technology trends on the soft error rate of combinational logic

by Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi, Ibm Technical, Contacts John Keaty, Rob Bell, Ram Rajamony , 2002
"... This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. Th ..."
Abstract - Cited by 374 (8 self) - Add to MetaCart
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs

Definitional Trees

by Sergio Antoy - In Proc. of the 3rd International Conference on Algebraic and Logic Programming , 1992
"... . Rewriting is a computational paradigm that specifies the actions, but not the control. We introduce a hierarchical structure representing, at a high level of abstraction, a form of control. Its application solves a specific problem arising in the design and implementation of inherently sequential, ..."
Abstract - Cited by 158 (40 self) - Add to MetaCart
. Rewriting is a computational paradigm that specifies the actions, but not the control. We introduce a hierarchical structure representing, at a high level of abstraction, a form of control. Its application solves a specific problem arising in the design and implementation of inherently sequential

Tree Arbiter with Nearest-Neighbour Scheduling

by Isi Mitrani, Alex Yakovlev , 1997
"... A tree arbiter designed to minimize the average delay between consecutive allocations of a contentious resource is described and evaluated. The idea is to divide the competing users into nested clusters corresponding to sub-trees of varying size, and to keep the resource within the smallest cluste ..."
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A tree arbiter designed to minimize the average delay between consecutive allocations of a contentious resource is described and evaluated. The idea is to divide the competing users into nested clusters corresponding to sub-trees of varying size, and to keep the resource within the smallest

Arbiters: Design ideas and coding styles

by Matt Weber
"... Arbiters exist in nearly every logic design. This paper will present several design ideas for effectively interfacing to an arbiter and investigate coding styles for some common arbitration schemes. Many systems exist in which a large number of requesters must access a common resource. The common re ..."
Abstract - Cited by 7 (0 self) - Add to MetaCart
resource may be a shared memory, a networking switch fabric, a specialized state machine, or a complex computational element. An arbiter is required to determine how the resource is shared amongst the many requesters. When putting an arbiter into a design, many

Learning Arbiter and Combiner Trees from Partitioned Data for Scaling Machine Learning

by Philip K. Chan, Salvatore J. Stolfo - In Proceedings of the First International Conference on Knowledge Discovery and Data Mining , 1995
"... Knowledge discovery in databases has become an increasingly important research topic with the advent of wide area network computing. One of the crucial problems we study in this paper is how to scale machine learning algorithms, that typically are designed to deal with main memory based datasets, to ..."
Abstract - Cited by 44 (7 self) - Add to MetaCart
, which are learned from subsets of the data, so that we scale efficiently to larger learning problems, and boost the accuracy of the constituent classifiers if possible. In this paper we compare the arbiter tree strategy to a new but related approach called the combiner tree strategy.

Measurements on a High Speed Arbiter

by Kinniment Technical Report, D J Kinniment , 2000
"... Measurements on a submicron CMOS arbiter implementation are presented. Using two uncorrelated asynchronous inputs to the arbiter effective time differences between requests of as low as 10 -18 sec can be obtained. The metastbility time of the arbiter is plotted against input request time differenc ..."
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Measurements on a submicron CMOS arbiter implementation are presented. Using two uncorrelated asynchronous inputs to the arbiter effective time differences between requests of as low as 10 -18 sec can be obtained. The metastbility time of the arbiter is plotted against input request time

Point-to-point connectivity between neuromorphic chips using address-events

by Kwabena A. Boahen - IEEE Trans. Circuits Syst. II , 2000
"... Abstract — I discuss connectivity between neuromorphic chips, which use the timing of fixed-height, fixed-width, pulses to encode information. Address-events—log2 (N)-bit packets that uniquely identify one of N neurons—are used to transmit these pulses in real-time on a random-access, time-multiplex ..."
Abstract - Cited by 128 (19 self) - Add to MetaCart
the arbitered channel with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, I show how the overhead of arbitrating, and encoding and decoding, can be reduced in area

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chips

by E. Rijpkema, K. G. W. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen, P. Wielage, E. Waterlander , 2003
"... Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. In this paper we show that guaranteed services are essentia ..."
Abstract - Cited by 155 (15 self) - Add to MetaCart
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. In this paper we show that guaranteed services
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