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CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit

by Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee - IN PROCEEDINGS OF THE 27TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE , 2000
"... Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline of an aggres ..."
Abstract - Cited by 109 (1 self) - Add to MetaCart
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline

The Chimera Reconfigurable Functional Unit

by Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao , 2004
"... By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host proce ..."
Abstract - Cited by 190 (19 self) - Add to MetaCart
processor itself. With direct access to the host processor’s register file, the system enables the creation of multi-operand instructions and a speculative execution model key to high-performance, general-purpose reconfigurable computing. Chimaera also supports multi-output functions and utilizes partial

A High-Performance Microarchitecture with Hardware-Programmable Functional Units

by Rahul Razdan, Michael D. Smith - In Proceedings of the 27th Annual International Symposium on Microarchitecture , 1994
"... This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of t ..."
Abstract - Cited by 221 (1 self) - Add to MetaCart
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set

DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design

by Todd M. Austin - In Proc. 32nd Annual Intl. Symp. on Microarchitecture , 1999
"... Building a high-petformance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To&rther complicate this task, deep submicro ..."
Abstract - Cited by 374 (15 self) - Add to MetaCart
of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. Thefunctional checker verifies the correctness of the core processor’s computation, only permitting correct results to commit. Overall design cost can

Larrabee: a many-core x86 architecture for visual computing

by Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Toni Juan, Pat Hanrahan - In SIGGRAPH ’08: ACM SIGGRAPH 2008 papers , 2008
"... Abstract 123 This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector proces ..."
Abstract - Cited by 279 (12 self) - Add to MetaCart
processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A

CHIMAERA: Integrating a Reconfigurable Unit into a High-Performance, Dynamically-Scheduled Superscalar Processor

by Zhi Alex Ye, Andreas Moshvos, Scott Hauck, Nagaraj Shenoy, Prithviraj Banerjee
"... We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline of an aggressive, dynamically-scheduled superscalar processor. We discuss the Chimaera C compiler that automatically maps computations for execution in t ..."
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We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline of an aggressive, dynamically-scheduled superscalar processor. We discuss the Chimaera C compiler that automatically maps computations for execution

Wide-Area Group Membership for Tightly-Coupled Services

by Kevin C. Webb, Bhanu C. Vattikonda, Kenneth Yocum, Alex C. Snoeren
"... Today’s large-scale services generally exploit looselycoupled architectures that restrict functionality requiring tight cooperation (e.g., leader election, synchronization, and reconfiguration) to a small subset of nodes. In contrast, this work presents a way to scalably deploy tightlycoupled distri ..."
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Today’s large-scale services generally exploit looselycoupled architectures that restrict functionality requiring tight cooperation (e.g., leader election, synchronization, and reconfiguration) to a small subset of nodes. In contrast, this work presents a way to scalably deploy tightlycoupled

Mapping Methods for the Chimaera Reconfigurable Functional Unit

by Katherine Nelson, Scott Hauck , 1997
"... In this paper we examine how the Chimaera Reconfigurable Functional Unit can be used to speed up program execution. We investigate a graphical skeletonization (object thinning) algorithm for this purpose. First, we will show how an assembly language post-processor or very primitive compiler could au ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
In this paper we examine how the Chimaera Reconfigurable Functional Unit can be used to speed up program execution. We investigate a graphical skeletonization (object thinning) algorithm for this purpose. First, we will show how an assembly language post-processor or very primitive compiler could

: A High-Performance Architecture

by For Run-Time Reconfiguration, Don Davis , 1998
"... Recent FPGA architectures have shown an increased emphasis on run-time reconfiguration, or the ability to rapidly change the functionality of the FPGA to sequentially accommodate large processing tasks. In addition, partial reconfiguration allows for the reconfiguration of a portion of the FPGA whil ..."
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management of the reconfigurable resources, interface to the host processor and data movement. In this paper, we will describe the architecture, design and applicability of the ACEcard, a high performance reconfigurable co-processor. The ACEcard contains reconfigurable resources as well as an embedded

Resource-aware Video Processing on Tightly-Coupled Processor Arrays

by Vahid Lari, Frank Hannig, Shravan Muddassani, Boris Kuzmin, Jürgen Teich
"... To meet the ever increasing computational needs, there is a strong trend towards research in many-core architectures. They offer a high degree of parallelism and achieve a better energy efficiency compared with traditional single processor solutions. Consequently, existing centralized resource manag ..."
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claim and reserve resources (invade), employ them for parallel execution (infect), and finally release them (retreat). We present a class of highly parameterizable and programmable processor array architectures [1], which we recently augmented by dedicated units for hardware-accelerated decentralized
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