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CAMA: A Predictable Cache-Aware Memory Allocator

by unknown authors
"... Abstract—General-purpose dynamic memory allocation al-gorithms strive for small memory fragmentation and good average-case response times. Hard real-time settings, in con-trast, place different demands on dynamic memory allocators: worst-case response times are more important than average-case respo ..."
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, and allocations are cache-set directed, i.e., allocated memory is guaranteed to be mapped to a given cache set. The latter two are necessary to enable a subsequent precise static cache analysis. Keywords-Dynamic storage allocation; WCET analysis; pre-dictability I.

CAMA: Cache-Aware Memory Allocation for WCET Analysis

by Jörg Herter, Reinhard Wilhelm
"... Abstract—Current WCET analyses do not support dynamic memory allocation. This is mainly due to the unpredictability of the cache performance if standard memory allocators are used. We present a novel dynamic memory allocator that makes cache performance predictable and (de)allocates memory in consta ..."
Abstract - Cited by 12 (4 self) - Add to MetaCart
Abstract—Current WCET analyses do not support dynamic memory allocation. This is mainly due to the unpredictability of the cache performance if standard memory allocators are used. We present a novel dynamic memory allocator that makes cache performance predictable and (de)allocates memory

Composable memory transactions

by Tim Harris, Mark Plesko, Avraham Shinnar, David Tarditi - In Symposium on Principles and Practice of Parallel Programming (PPoPP , 2005
"... Atomic blocks allow programmers to delimit sections of code as ‘atomic’, leaving the language’s implementation to enforce atomicity. Existing work has shown how to implement atomic blocks over word-based transactional memory that provides scalable multiprocessor performance without requiring changes ..."
Abstract - Cited by 506 (42 self) - Add to MetaCart
changes to the basic structure of objects in the heap. However, these implementations perform poorly because they interpose on all accesses to shared memory in the atomic block, redirecting updates to a thread-private log which must be searched by reads in the block and later reconciled with the heap when

TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems

by Pete Keleher , Alan L. Cox, Sandhya Dwarkadas, Willy Zwaenepoel - IN PROCEEDINGS OF THE 1994 WINTER USENIX CONFERENCE , 1994
"... TreadMarks is a distributed shared memory (DSM) system for standard Unix systems such as SunOS and Ultrix. This paper presents a performance evaluation of TreadMarks running on Ultrix using DECstation-5000/240's that are connected by a 100-Mbps switch-based ATM LAN and a 10-Mbps Ethernet. Ou ..."
Abstract - Cited by 527 (17 self) - Add to MetaCart
TreadMarks is a distributed shared memory (DSM) system for standard Unix systems such as SunOS and Ultrix. This paper presents a performance evaluation of TreadMarks running on Ultrix using DECstation-5000/240's that are connected by a 100-Mbps switch-based ATM LAN and a 10-Mbps Ethernet

Cache-Aware Scheduling and Analysis for Multicores ∗

by Nan Guan, Martin Stigge, Wang Yi, Ge Yu
"... The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms; the way of handling the on-chip shared resources such as L2 cache may have a significant impact on the timing predictab ..."
Abstract - Cited by 35 (5 self) - Add to MetaCart
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms; the way of handling the on-chip shared resources such as L2 cache may have a significant impact on the timing

Treadmarks: Shared memory computing on networks of workstations

by Cristiana Amza, Alan L. Cox, Hya Dwarkadas, Pete Keleher, Honghui Lu, Ramakrishnan Rajamony, Weimin Yu, Willy Zwaenepoel - Computer , 1996
"... TreadMarks supports parallel computing on networks of workstations by providing the application with a shared memory abstraction. Shared memory facilitates the transition from sequential to parallel programs. After identifying possible sources of parallelism in the code, most of the data structures ..."
Abstract - Cited by 484 (37 self) - Add to MetaCart
TreadMarks supports parallel computing on networks of workstations by providing the application with a shared memory abstraction. Shared memory facilitates the transition from sequential to parallel programs. After identifying possible sources of parallelism in the code, most of the data structures

The Elements of Statistical Learning -- Data Mining, Inference, and Prediction

by Trevor Hastie, Robert Tibshirani, Jerome Friedman
"... ..."
Abstract - Cited by 1320 (13 self) - Add to MetaCart
Abstract not found

Efficient implementation of a BDD package

by Karl S. Brace, Richard L. Rudell, Randal E. Bryant - In Proceedings of the 27th ACM/IEEE conference on Design autamation , 1991
"... Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
Abstract - Cited by 500 (9 self) - Add to MetaCart
implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong carwnical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory funcfion for the recursive ITE algorithm is implemented using a hash-based cache

Exokernel: An Operating System Architecture for Application-Level Resource Management

by Dawson R. Engler, M. Frans Kaashoek, James O’toole , 1995
"... We describe an operating system architecture that securely multiplexes machine resources while permitting an unprecedented degree of application-specific customization of traditional operating system abstractions. By abstracting physical hardware resources, traditional operating systems have signifi ..."
Abstract - Cited by 724 (24 self) - Add to MetaCart
Aegis operations are 10–100 times faster than Ultrix,a mature monolithic UNIX operating system. ExOS implements processes, virtual memory, and inter-process communication abstractions entirely within a library. Measurements show that ExOS’s application-level virtual memory and IPC primitives are 5

WCET-driven Cache-aware Memory Content Selection

by Sascha Plazar, Paul Lokuciejewski, Peter Marwedel
"... Abstract—Caches are widely used to bridge the increasingly growing gap between processor and memory performance. They store copies of frequently used parts of the slow main memory for faster access. Static analysis techniques allow the estimation of the worstcase cache behavior and enable the comput ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
new WCET-driven cache-aware memory content selection algorithm, which allocates functions whose WCET highly benefits from a cached execution to cached memory areas. Vice versa, rarely used functions which do not benefit from a cached execution are allocated to noncached memory areas. As a result
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