### Table 2: Testability and literal count comparisons of multilevel implementations

1992

"... In PAGE 27: ... Multilevel logic circuits are of much greater utility. In Table2 , we compare literal counts and path-delay-fault testabilities obtained using algebraic factorization and unconstrained multilevel lo- gic optimization on the di erent examples. Unconstrained multilevel optimization implies that the initial two-level network was multiple-output minimized and Boolean factorization was used during logic optimization.... In PAGE 27: ... Unconstrained multilevel optimization implies that the initial two-level network was multiple-output minimized and Boolean factorization was used during logic optimization. Algebraic factorization was used on the circuits produced by the single-output minimization ( Table2 ). A modi ed version of the program mis [2] was used in both cases.... ..."

Cited by 11

### Table 1: Testability and area comparisons of two-level implementations

1992

"... In PAGE 27: ...heorems 7.1 and 7.2 may easily be generalized. 8 Experimental Results We present experimental results using an ENF-based program for analyzing the delay-fault testability of multilevel circuits, and preliminary experimental results obtained via algebraic factorization to retain robust path-delay-fault testability. We chose several examples from the MCNC Benchmark set, whose statistics and path-delay- fault testabilities under a two-level implementation are summarized in Table1 . The testabilities for single-output minimized and multiple-output minimized two-level representations were determined using an ENF-based analysis program.... ..."

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### Table 1. Pseudo-random testability bench

"... In PAGE 3: ... The number of LFSR bits was set to be equal to the number of CUT inputs. The results of a simulation of a selected set of benchmarks are shown in Table1 . The i column shows the number of the benchmark inputs (including the scan path for sequential circuits), range indicates the range of the encountered number of test patterns to fully test the circuit (in those 1000 samples), while the statistical average value is shown in the last column.... ..."

### Table 3: The axioms for boolean algebras.

1998

"... In PAGE 9: ... n28We have kept our numbering consistent with Groote and Ponse n281994an29; in their setting Sum2 den0cnes n0b-conversion.n29 Let n06 be a pCRL-signature, then the pCRL-theory n05 n06 for n06 consists of the axioms depicted in Table 2 and the axioms for boolean algebras depicted in Table3 . A n06-algebra A is called a pCRL-algebra if A j=n05 n06... ..."

### Table 1: The axioms for boolean algebras.

1999

"... In PAGE 8: ... 3. Data speci cations In the theory pCRL, the data must be given by means of a many-sorted equational speci cation D = h ; Ei that contains the axioms of boolean algebra (see Table1 ); such an equational speci cation is called a data speci cation. For easier explanation of our ideas we shall focuss on a certain kind of data speci cations that have a nice correspondence with theories of rst-order predicate logic.... In PAGE 8: ... We shall occasionally refer to the function declarations of the rst kind as relations, and to those of the second kind as functions. Let us x a data speci cation D = h ; Ei of this kind; we denote by Eb the set of axioms of sort b (it contains the axioms in Table1 ), and by Ed the set of axioms of sort d. We may regard as the rst-order language that has the relations of as relation symbols and the functions of as operation symbols.... ..."

### Table 4. Comparison of results between Karnaugh Maps plus Boolean algebra, Quine- McCluskey Procedure and EGP on the Katz problem.

### Table 3: The axioms of boolean algebras.

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### Table 1. Axioms of Boolean algebras

"... In PAGE 6: ...arbitrary subset of A. The axioms of BA given in Table1 have been taken from [18]. Several al- ternatives for this axiomatization can be found in the literature.... ..."

### Table 4: Comparison with results reported in [15] Even though the path count in our resynthesized cir- cuits reduces, the path delay fault testability T might not improve since in our procedure it is hard to control the type of paths added into the design. To improve the path delay testability we use test point insertion. Re- sults on the test point insertion for reducing the number of long FS paths are shown in Table 5. The value T represents the path delay testability with respect to long (longer that 85% of the clock period) functional irredun- dant paths, i.e., T =

in Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

1997

"... In PAGE 4: ... Even though the procedure Perturb-Simplify gives a slightly larger reduction in the number of 2-input gates than our path reduction algorithm, the number of paths in 3 out of 4 shown cases is much higher than it was in the original circuit and in all cases higher than in our nal circuits. Table4 shows a comparison of our results for fully scanned, irredundant ISCAS89 sequential circuits with the results presented in [15]. To obtain similar origi- nal circuits as the ones used in [15] we have used [7] to remove initial redundancies in these circuits (when the number of paths/gates di er we show the numbers for the circuits used in [15] in parentheses).... ..."

Cited by 6

### Table 4: Testability results

1998

"... In PAGE 10: ...In Table4 , testability results for the circuits are presented. We compare the performance of TAO against HITEC [24], an efficient gate-level sequential test generator.... ..."

Cited by 8