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206,957
Hierarchical GateLevel Verification of SpeedIndependent Circuits
 In Asynchronous Design Methodologies
, 1995
"... This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite ..."
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Cited by 6 (3 self)
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This paper presents a method for the verification of speedindependent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flipflops) of the circuit. Despite
Sufficient Conditions for Correct GateLevel SpeedIndependent Circuits
 In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1994
"... We describe sufficient conditions for the correctness of speedindependent asynchronous circuits. The circuit specifications considered are determinate, allowing input choice but not output choice (arbitration). The circuit implementations considered are networks of singleoutput basic gates. A circ ..."
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Cited by 7 (2 self)
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We describe sufficient conditions for the correctness of speedindependent asynchronous circuits. The circuit specifications considered are determinate, allowing input choice but not output choice (arbitration). The circuit implementations considered are networks of singleoutput basic gates. A
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
Logic Decomposition of SpeedIndependent Circuits
 PROCEEDINGS OF THE IEEE
, 1999
"... ... This paper presents a new method for logic decomposition of speedindependent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches ..."
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Cited by 7 (1 self)
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... This paper presents a new method for logic decomposition of speedindependent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous
Estimation of Energy Consumption in SpeedIndependent Control Circuits
 IEEE Transactions on CAD
, 1995
"... : We describe a technique to estimate the energy consumed by speedindependent asynchronous (clockless) control circuits. Because speedindependent circuits are hazardfree under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent o ..."
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Cited by 8 (1 self)
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: We describe a technique to estimate the energy consumed by speedindependent asynchronous (clockless) control circuits. Because speedindependent circuits are hazardfree under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent
Estimation of Energy Consumption in SpeedIndependent Control Circuits
 IEEE Transactions on CAD
, 1995
"... We describe a technique to estimate the energy consumed by speedindependent asynchronous (clockless) control circuits. Because speedindependent circuits are hazardfree under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent of ..."
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We describe a technique to estimate the energy consumed by speedindependent asynchronous (clockless) control circuits. Because speedindependent circuits are hazardfree under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent
Technology Mapping for SpeedIndependent Circuits: Decomposition and Resynthesis
, 1997
"... This paper presents theory and practical implementation of a method for multilevel logic synthesis of speedindependent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (in ..."
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Cited by 25 (10 self)
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synthesis, but achieves also boolean simplification and sequential decomposition. The method allows sharing of decomposed logic. 1 Introduction Speedindependent circuits, originating from D.E. Muller's work [11], are hazardfree under the unbounded gate delay model. With recentprogress in developing
Synthesis of Speedindependent circuits from STGunfolding segment
 Proc. 34th ACM/IEEE Design Automation Conference
, 1997
"... This paper presents a novel technique for synthesis of speedindependent circuits. It is based on partial order representation of the state graph called STGunfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic implem ..."
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Cited by 4 (1 self)
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This paper presents a novel technique for synthesis of speedindependent circuits. It is based on partial order representation of the state graph called STGunfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic
Controlled and automatic human information processing
 I. Detection, search, and attention. Psychological Review
, 1977
"... A twoprocess theory of human information processing is proposed and applied to detection, search, and attention phenomena. Automatic processing is activation of a learned sequence of elements in longterm memory that is initiated by appropriate inputs and then proceeds automatically—without subjec ..."
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Cited by 841 (15 self)
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), and is controlled by the subject. A series of studies using both reaction time and accuracy measures is presented, which traces these concepts in the form of automatic detection and controlled, search through the areas of detection, search, and attention. Results in these areas are shown to arise from common
A New Look at the Conditions for the Synthesis of Speedindependent Circuits
 IN PROC. FIFTH GREAT LAKES SYMPOSIUM ON VLSI
, 1994
"... This technical report presents a set of sufficient conditions for the gatelevel synthesis of speedindependent circuits when constrained to a given class of gate libraries. Existing synthesis techniques are restricted to architectures that use simple ANDgates, and do not exploit the advantages of ..."
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Cited by 2 (2 self)
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This technical report presents a set of sufficient conditions for the gatelevel synthesis of speedindependent circuits when constrained to a given class of gate libraries. Existing synthesis techniques are restricted to architectures that use simple ANDgates, and do not exploit the advantages
Results 1  10
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206,957