"... In PAGE 5: ... (a) (b) PI PS PO NS NS PS NS PS 1 a slow-to-rise a slow-to-rise a slow-to-rise 2 3 PI PI PS PO NS NS PS NS PS 1 a slow-to-rise a slow-to-rise a slow-to-rise 2 3 PI FFs FFs Figure 9: Circuit model for test generation for k = 3. Table1 shows the results of these experiments. The experiments were performed for transition faults of size equal to one clock cycle.... ..."

"... In PAGE 26: ... However, some timing failures that are embedded in short paths may not cause delay faults at normal operating conditions. Table3 -1 lists the causes of timing failures and the possible testing techniques for detecting them. Although all of these failures may be detected by delay fault testing, the success of detection depends on the significance of the excessive delay in the defective circuit.... In PAGE 27: ...3.1 Causes and Failure Modes of Timing Failures Table3 -1 lists the causes of timing failures. Transmission gate opens occur when one of the transistors in a CMOS transmission gate is malfunctioning and cannot pass any signals.... In PAGE 28: ... Tunneling opens allow CUTs to be functional at low frequencies but cause failures at higher frequencies [Henderson 91]. Table3 -2 summarizes the failure modes of the timing failures described above. This chapter discusses how VLV testing can improve the detectability of timing failures that are caused by degraded signals and by transistors with lowered driving capabilities.... In PAGE 29: ... Table3 -2 Failure Modes of Timing Failures Causes Failure Modes Transmission gate opens Degraded signals Threshold voltage shifts Increased gate delays Slow-to-fall signals Diminished-drive gates Increased gate delays Slow-to-rise signals Slow-to-fall signals Gate oxide shorts Degraded signals Increased leakage Metal shorts Degraded signals Increased leakage Defective interconnect buffers Degraded signals Increased gate delays Increased RC delays Increased leakage Opens High resistance interconnects, via defects Increased RC delays Slow-to-rise signals Slow-to-fall signals Tunneling opens CUT fails at high frequencies 3.2 Voltage Dependence of CMOS Propagation Delay VLV testing is most effective in detecting delay flaws when the supply voltage is around the value where the propagation delay of a circuit starts to change significantly as the supply voltage is reduced.... In PAGE 31: ...5Vt, which is the same as the voltage range for VLV testing proposed in Chapter 2. Table3 -3 lists the delay ratios of WD and fault-free gates at different voltages for... In PAGE 32: ....6 m m technology can be found in Appendix B. As shown in Appendix B, we also used more complicated circuits to verify the conclusion. Figure 3-2 Voltage Dependence of the Change Rate of the Propagation Delay of a CMOS Inverter Table3 -3 WD Delay Ratios for the 0.8 m m Technology Vdd Vdd / Vtn Td(Vdd )* a TWD(Vdd)** Delay Ratio TWD(Vdd)/ Td(Vdd) 1.... In PAGE 35: ...nd the 0.6 m m technology are similar, only the results for the 0.6 m m technology are discussed in this dissertation. Table3 -4 shows the simulation results for the 0.6 m m technology.... In PAGE 36: ... Table3 -4 Delay Ratio between Faulty and Fault-Free High-Drive Gate in Fig. 3-3 for the 0.... ..."

"... In PAGE 7: ... 3 STATE OF THE ART IN NOCS This Section is intended to provide a big picture of the state of the art in network- on-chip propositions, as currently found in the available literature. The results of the review are summarized in Table1 . In this Table, each row corresponds to a NoC proposition that could be found about which significant qualitative and quantitative implementation data were made available.... In PAGE 7: ... Each NoC defining parameter is described in detail below, together with an evaluation of the relative merits of each reviewed NoC proposition. The last row of Table1 corresponds to the NoC infrastructure proposed here. 2 Data presented in Table 1 is the preliminary result of publication analysis only.... In PAGE 7: ... The last row of Table 1 corresponds to the NoC infrastructure proposed here. 2 Data presented in Table1 is the preliminary result of publication analysis only. The authors are currently contacting the authors of each NoC proposition to obtain further data, and expect to provide a ... In PAGE 8: ... The exception is the aSOC NoC [18], where the definition of the route each message follows is fixed at the time of hardware synthesis. Two connected concepts, network topology and switching strategy are the subject of the first column in Table1 . The predominant network topology in the literature is the 2D Mesh.... In PAGE 9: ... The second important quantitative parameter of NoC switches is the flit size. From Table1 it is possible to classify approaches in two groups, those focusing on future SoC technologies and those adapted to existing limitations. The first group includes the proposals of Dally [19] and Kumar [5], where switching channels are supposed to be 300-wire wide without significantly affecting the overall SoC area.... In PAGE 9: ... The works providing a NoC prototype, Marescaux [23] and the one proposed here, have the smallest flit sizes, 16 and 8 bits, respectively. The next parameter in Table1 is the switch buffering strategy. Most NoCs employ input queue buffers.... In PAGE 9: ... A NoC with a custom IP-switch interface, such as [23], is less apt to aggregate third party IPs to the design in a timely manner. The two most prominent interface standards, VCI and OCP are each used by two of the NoC proposals presented in Table1 . The Proteo [25][26][27] and SPIN [16][17] NoCs declare to use VCI, while Sgroi [20] and Hermes [28] employ OCP.... In PAGE 10: ... Adoption of NoCs is then tied to these quantitative assessments and to the ease with which designers are provided to evaluate the NoC approach in real designs. Estimated peak performance, presented in the sixth column of Table1 , is a parameter that needs further analysis to provide a meaningful comparison among different NoCs. In this way, this column displays different units for different NoCs.... ..."

"... In PAGE 6: ...7 1615 88.4 1886 Table1 : Transition fault results for at-speed schemes. Combining slow-fast-slow and at-speed testing schemes for slow testers could result in higher fault coverages and reduced test application times.... ..."

"... In PAGE 3: ... Based on the network topology, we use routers with 3, 4, 5 or 6 ports. The area occupied by the routers, as a function of the number of ports, is summarized in Table2 . Although none of the routers is optimized for area, their area overhead is smaller than the overhead incurred by the dedicated links and network interfaces of the P2P implementation; we discuss this in detail in Section 3.... ..."

"... In PAGE 3: ... Based on the network topology, we use routers with 3, 4, 5 or 6 ports. The area occupied by the routers, as a function of the number of ports, is summarized in Table2 . Although none of the routers is optimized for area, their area overhead is smaller than the overhead incurred by the dedicated links and network interfaces of the P2P implementation; we discuss this in detail in Section 3.... ..."

"... In PAGE 4: ... Clearly some chips have timing problems and it makes sense to try some type of delay testing. Table4 shows the results of applying 12 test sets that do not rely directly on the SSF model. Nine of these target delay faults.... In PAGE 4: ... The techniques used to derive this table were explained at ITC apos;98 [2]. For the test sets that we were able to obtain, the N-detect sets seem to perform better for comparable test length than any of the test sets in Table4 . The remaining items, IDDq and VLV, will be ... In PAGE 5: ... 3. The results in Table4 were obtained using at- speed testing. To our surprise, there were more test escapes when two-pattern testing was used.... In PAGE 6: ... IDDq tests can be used to identify non-functional (failed) chips as well as weak chips. As shown in Table4 , 15 failed chips escaped our IDDq tests. A paper at VTS apos;98 [11], describes the details of this study.... ..."