Extremely narrow and bulk-like p-type InAs-Si nanowire TFETs are studied using (i) a full-band and atomistic quantum transport simulator based on the sp3d5s tight-binding model and (ii) a drift-diffusion TCAD tool. As (iii) option, a two-band model and the WKB approximation have been adapted

and vertical band-to-band tunneling paths. TFETs with only vertical tunneling components are also investigated. Our findings suggest that InAs-Si 2D-2D TFETs might offer a device solution with both steep sub-thermal sub-threshold swing (SS) and high ON-current. In the best case of an extremely thin InAs-Si 2D

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Botiingen Foundation, andpttt.!.,.: b % / ,.,;:,c,m B<,.ik.*, second

characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show

Abstract—This paper presents a TCAD study on the performance of Si, InAs, and Si-InAs tunnel diodes and tunnel FETs. Comparative NEGF simulations of short InAs homo-diodes and experimental data on Si homo-diodes serve to calibrate the tunnel models for InAs and Si. Two workarounds for the case

bS Supporting Information ABSTRACT: We report on the electrical characterization of one-sided p +-si/n-InAs nanowire heterojunction tunnel diodes to provide insight into the tunnel process occurring in this highly lattice mismatched material system. The lattice mismatch gives rise to dislocations

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, and its scattering-dominated and scattering-free versions are introduced. Remarks are also given about the underlying mathematics and numerics. A variety of ap-plications of the theory to both quantum confinement and quantum tunneling situations are then reviewed. In doing so, particular emphasis is put