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501
An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization
, 2007
"... We present an efficient framework for dynamic reconfiguration of application-specific instruction-set customization. A key component of this framework is an iterative algorithm for temporal and spatial partitioning of the loop kernels. Our algorithm maximizes the performance gain of an application w ..."
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Cited by 7 (3 self)
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We present an efficient framework for dynamic reconfiguration of application-specific instruction-set customization. A key component of this framework is an iterative algorithm for temporal and spatial partitioning of the loop kernels. Our algorithm maximizes the performance gain of an application
Pin: building customized program analysis tools with dynamic instrumentation
- IN PLDI ’05: PROCEEDINGS OF THE 2005 ACM SIGPLAN CONFERENCE ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION
, 2005
"... Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we have developed a new instrumentation system called Pin. Our goals are to provide easy-to-use, portable, transparent, and eff ..."
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Cited by 991 (35 self)
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, and efficient instrumentation. Instrumentation tools (called Pintools) are written in C/C++ using Pin’s rich API. Pin follows the model of ATOM, allowing the tool writer to analyze an application at the instruction level without the need for detailed knowledge of the underlying instruction set. The API
An Efficient Retargetable Framework for Instruction-Set Simulation
- in Proc. IEEE/ACM/IFIP Int. Conf. Hardware/Software Codesign & System Synthesis
, 2003
"... Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high performance simulation, the increasing variety of available architectures makes retargetability a critical feature o ..."
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Cited by 23 (7 self)
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of an instruction-set simulator. Retargetability requires generic models while high performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability
An Efficient Retargetable Framework for Instruction-Set Simulation
- in Proc. IEEE/ACM/IFIP Int. Conf. Hardware/Software Codesign & System Synthesis
, 2003
"... Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high performance simulation, the increasing variety of available architectures makes retargetability a critical feature o ..."
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of an instruction-set simulator. Retargetability requires generic models while high performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability
ReXSim: A Retargetable Framework for Instruction-Set Architecture Simulation
, 2003
"... Instruction-set simulators are an integral part of today's processor and software design process. Due to increasing complexity of the architectures and time-to-market pressure, performance and retargetability are the most important features of an instruction-set simulator. Dynamic behavior of a ..."
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Cited by 1 (0 self)
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Instruction-set simulators are an integral part of today's processor and software design process. Due to increasing complexity of the architectures and time-to-market pressure, performance and retargetability are the most important features of an instruction-set simulator. Dynamic behavior
Efficient Design-space Exploration of Custom Instruction-set Extensions
, 2010
"... Customization of processors with instruction set extensions (ISEs) is a technique that improves performance through parallelization with a reasonable area over-head, in exchange for additional design effort. This thesis presents a collection of novel techniques that reduce the design effort and cost ..."
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Customization of processors with instruction set extensions (ISEs) is a technique that improves performance through parallelization with a reasonable area over-head, in exchange for additional design effort. This thesis presents a collection of novel techniques that reduce the design effort
A Dynamic Instruction Set Computer
- Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines
, 1995
"... A Dynamic Instruction Set Computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing p ..."
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Cited by 135 (5 self)
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A Dynamic Instruction Set Computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing
Reconfigurable Instruction Set Processors: A survey
- IEEE Transactions on Software Engineering
, 2000
"... Future interactive multimedia applications are characterized by a large variety of compression algorithms with highly parallel nested loops. It will not be efficient to design custom processors suitable for this wide range of applications due to the uncertainty on what is going to be executed. Inste ..."
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Cited by 31 (3 self)
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. Instead, we must find ways to cope with such dynamic and compute intensive tasks. Reconfigurable instruction set processors can cope with this dynamism by specializing the hardware to the algorithm at hand at runtime. They achieve this thanks to a flexible fabric of coarse-grained processing elements
Processor acceleration through automated instruction set customization
- In MICRO
, 2003
"... Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or co-processors), and the corresponding instructions, are added to ..."
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Cited by 95 (5 self)
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, we present the design of a system to automate the instruction set customization process. A dataflow graph design space exploration engine efficiently identifies profitable computation subgraphs from which to create custom hardware, without artificially constraining their size or shape. The system
Dytan: A Generic Dynamic Taint Analysis Framework
- in Proceedings of the International Symposium on Software Testing and Analysis
, 2007
"... Dynamic taint analysis is gaining momentum. Techniques based on dynamic tainting have been successfully used in the context of application security, and now their use is also being explored in different areas, such as program understanding, software testing, and debugging. Unfortunately, most existi ..."
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Cited by 137 (5 self)
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-flow and control-flow based tainting conservatively, and (3) does not rely on any customized runtime system. We also present DYTAN, an implementation of our framework that works on x86 executables, and a set of preliminary studies that show how DYTAN can be used to implement different tainting-based approaches
Results 1 - 10
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501