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Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking

by Shaz Qadeer , 2001
"... The memory model of a shared-memory multiprocessor is a contract between the designer and programmer of the multiprocessor. The sequential consistency memory model specifies a total order among the memory (read and write) events performed at each processor. A trace of a memory system satisfies seque ..."
Abstract - Cited by 29 (1 self) - Add to MetaCart
The memory model of a shared-memory multiprocessor is a contract between the designer and programmer of the multiprocessor. The sequential consistency memory model specifies a total order among the memory (read and write) events performed at each processor. A trace of a memory system satisfies

Extending The Dimensions of Consistency: Spatial Consistency and Sequential Segments

by James Griffioen, Rajendra Yavatkar, Raphael Finkel - University Of Kentucky , 1994
"... The Unify system is exploring scalable approaches for designing distributed multicomputers that support a shared memory paradigm. To achieve massive scalability, unify employs highly efficient communication protocols to support new weak consistency sharing models. In particular, Unify introduces the ..."
Abstract - Cited by 3 (2 self) - Add to MetaCart
The Unify system is exploring scalable approaches for designing distributed multicomputers that support a shared memory paradigm. To achieve massive scalability, unify employs highly efficient communication protocols to support new weak consistency sharing models. In particular, Unify introduces

Post-Silicon Validation of Multiprocessor Memory Consistency

by Student Member, IEEE Biruk W Mammo , Senior Member, IEEE Valeria Bertacco , Member, IEEE Andrew Deorio , Ilya Wagner
"... Abstract-Shared-memory chip-multiprocessor (CMP) architectures define memory consistency models that establish the ordering rules for memory operations from multiple threads. Validating the correctness of a CMP's implementation of its memory consistency model requires extensive monitoring and ..."
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Abstract-Shared-memory chip-multiprocessor (CMP) architectures define memory consistency models that establish the ordering rules for memory operations from multiple threads. Validating the correctness of a CMP's implementation of its memory consistency model requires extensive monitoring

1Lamport Clocks: Reasoning About Shared Memory Correctness1

by Daniel J. Sorin, Manoj Plakal, Mark D. Hill, Anne E. Condon
"... Modern shared memory implementations use many complex, interacting optimizations, forcing industrial product groups to spend much more effort in verification than in design. Current formal verification techniques are somewhat non-intuitive to system designers and verifiers, and these formal methods ..."
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to create a total order of events. We modestly extend Lamport’s logical clock work from distributed systems and apply it to shared memory systems. We use these so-called Lamport clocks to timestamp events and thereby create a total order. This total order can then be examined to see if it satisfies

Using Lamport Clocks to Reason About Relaxed Memory Models

by Anne E. Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin - In Proceedings of the 5th International Symposium on High Performance Computer Architecture , 1999
"... Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport’s logical clocks for showing that multiprocessors can implement sequential consistency (SC) with an SGI Origin 2000-like directory protocol and a Sun Gigapla ..."
Abstract - Cited by 28 (6 self) - Add to MetaCart
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport’s logical clocks for showing that multiprocessors can implement sequential consistency (SC) with an SGI Origin 2000-like directory protocol and a Sun

Lamport Clocks: Verifying a Directory Cache-Coherence Protocol

by Manoj Plakal, Daniel J. Sorin, Anne E. Condon, Mark D. Hill - In Proceedings of the 10th Annual ACM Symposium on Parallel Architectures and Algorithms , 1998
"... Modern shared-memory multiprocessors use complex memory system implementations that include a variety of non-trivial and interacting optimizations. More time is spent in verl$ving the correctness of such implementations than in designing the system. In particular; large-scale Distributed Shared Memo ..."
Abstract - Cited by 44 (14 self) - Add to MetaCart
Memory (DSM) systems usually rely on a directory cache-coherence protocol to provide the illusion of a sequentially consistent shared address space. Verifying that such a distributed protocol satisfies sequential consistency is a dificult task. Current formal protocol verification techniques [18

Isotach Networks

by Paul F. Reynolds, Jr., Craig Williams, Raymond R. Wagner - IEEE Transactions on Parallel and Distributed Systems , 1997
"... We introduce a class of networks called isotach networks designed to reduce the cost of concurrency control in asynchronous computations. Isotach networks support several properties important to the correct execution of parallel and distributed computations: atomicity, causal message delivery, se ..."
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, sequential consistency, and memory coherence in systems in which shared data can replicate and migrate. They allow processes to execute atomic actions without locks and to pipeline memory accesses without sacrificing sequential consistency. Isotach networks can be implemented in a wide variety

1 Using Lamport Clocks to Reason About Relaxed Memory Models

by Anne E. Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorincomputer Sciences Department
"... AbstractCache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work pro-posed an extension of Lamport's logical clocks for showing that multiprocessors can implement sequential consistency(SC) with an SGI Origin 2000-like directory protocol and ..."
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AbstractCache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work pro-posed an extension of Lamport's logical clocks for showing that multiprocessors can implement sequential consistency(SC) with an SGI Origin 2000-like directory protocol

Using Lamport Clocks to Reason About Relaxed Memory Models

by Anne Condon Mark, Mark D. Hill, Manoj Plakal, Daniel J. Sorin , 1999
"... Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing that multiprocessors can implement sequential consistency (SC) with an SGI Origin 2000-like directory protocol and a Sun Gi ..."
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Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing that multiprocessors can implement sequential consistency (SC) with an SGI Origin 2000-like directory protocol and a Sun

Calvin: Deterministic or Not? Free Will to Choose

by Derek R. Hower, Polina Dudnik, Mark D. Hill, David A. Wood
"... Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suffer from hard-toreproduce hiesenbugs. We introduce Calvin, a shared memory model capable of executing in a conventional no ..."
Abstract - Cited by 23 (1 self) - Add to MetaCart
nondeterministic mode when performance is paramount and a deterministic mode when execution repeatability is important. Unlike prior hardware proposals for deterministic execution, Calvin exploits the flexibility of a memory consistency model weaker than sequential consistency. Specifically, Calvin logically
Results 1 - 10 of 46