, and customize code sequences for the underlying microarchitecture. This thesis presents a hardware mechanism for generating and deploying run-time optimized code. The system exploits program execution phasing by automatically detecting and optimizing the instruction sequences that comprise the phase, called a

Run-time code generation (RTCG) has been shown to be an effective optimiza-tion. Systems such as DyC, ’C, Tempo, and Fabius have demonstrated order of magnitude improvements on benchmark programs. In addition, by using binding time analyses, the benefits of RTCG can be obtained with minimal

. On-line tools for parallel and distributed programs require a facility to observe and possibly manipulate the programs' run-time behavior, a so called monitoring system. Currently, most tools use proprietary monitoring techniques that are incompatible to each other and usually apply only

Converting a conventional contract into an electronic equivalent that can be executed and enforced by computers is a challenging task. The difficulties are caused by the ambiguities that the original humanoriented text is likely to contain. The conversion process involves the conversion

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and applies a fully parallel data dependence test to check for any unsatisfied data dependencies; if the test fails, then the loop is re--executed serially. We will present the principles of the design and implementation of a compiler that employs both run-time and static techniques to parallelize dynamic

space fails because communication can only be determined at run-time. However, in many of these applications the communication pattern repeats for every iteration. Therefore, equivalent optimizations to the regular case can be achieved with a combination of run-time support (RTS) and compiler analysis.