Results 1 - 10 of 17

Data Sheet Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

by unknown authors
"... Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy) Zero delay operation Input-to-output edge timing: <150 ps 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps ..."
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of period of VCO output divider Output-to-output skew: <50 ps Duty-cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: <200 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz Distribution phase noise floor: −160 dBc/Hz Digital lock

MPEG-4 for Interactive Low-delay Real-time Communication

by Olaf L, Gary Minden , 2003
"... ii Internet broadcasting techniques are wide spread and have been the focus off many research projects. Due to high transmission delays these systems often lack interactivity. This thesis introduces a new streaming system to deliver real-time video and audio data with low-delays across the Internet. ..."
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ii Internet broadcasting techniques are wide spread and have been the focus off many research projects. Due to high transmission delays these systems often lack interactivity. This thesis introduces a new streaming system to deliver real-time video and audio data with low-delays across the Internet

On-chip VCO tunes from 2.30 GHz to 2.65 GHz

by Low Phase Noise, Phase-locked Loop (pll
"... External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock det ..."
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The AD9516-11 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9516-1 emphasizes low jitter and phase noise

On-chip VCO tunes from 1.45 GHz to 1.80 GHz

by Low Phase Noise, Phase-locked Loop (pll
"... External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock det ..."
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The AD9516-41 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9516-4 emphasizes low jitter and phase noise

On-chip VCO tunes from 2.05 GHz to 2.33 GHz

by Low Phase Noise, Phase-locked Loop (pll
"... External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock det ..."
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The AD9516-21 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9516-2 emphasizes low jitter and phase noise

FUNCTIONAL BLOCK DIAGRAM

by unknown authors
"... Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy) Zero delay operation Input-to-output edge timing: <150 ps Dual VCO dividers 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 ..."
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fs Digital lock detect Nonvolatile EEPROM stores configuration settings SPI- and IC-compatible serial control port Dual PLL architecture PLL1 Low bandwidth for reference input clock cleanup with external VCXO Phase detector rate of 300 kHz to 75 MHz Redundant reference inputs Auto and manual

FEATURES

by unknown authors
"... Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy) Zero delay operation Input-to-output edge timing: <±150 ps 6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 6 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps o ..."
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of period of VCO output divider Output-to-output skew: <±50 ps Duty-cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: <200 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz Distribution phase noise floor: −160 dBc/Hz Digital lock

1Sub-Nyquist Sampling: Bridging Theory and Practice

by Moshe Mishali, Yonina C. Eldar
"... [ A review of past and recent strategies for sub-Nyquist sampling] Signal processing methods have changed substantially over the last several decades. In modern applications, an increasing number of functions is being pushed forward to sophisticated software algorithms, leaving only delicate finely- ..."
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-tuned tasks for the circuit level. Sampling theory, the gate to the digital world, is the key enabling this revolution, encompassing all aspects related to the conversion of continuous-time signals to discrete streams of numbers. The famous Shannon-Nyquist theorem has become a landmark: a mathematical

1A Sub-Nyquist Radar Prototype: Hardware and Algorithms

by Eliahu Baransky, Gal Itzhak, Idan Shmuel, Noam Wagner, Eli Shoshan, Yonina C. Eldar
"... Abstract—Traditional radar sensing typically employs matched filtering between the received signal and the shape of the transmitted pulse. Matched filtering is conventionally carried out digitally, after sampling the received analog signals. Here, principles from classic sampling theory are generall ..."
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Abstract—Traditional radar sensing typically employs matched filtering between the received signal and the shape of the transmitted pulse. Matched filtering is conventionally carried out digitally, after sampling the received analog signals. Here, principles from classic sampling theory

Guaranteeing Communication Quality in Real World WSN Deployments

by Fbk-irst Bruno, Kessler Foundation, Matteo Ceriotti, Dr. Amy, L. Murphy, Bruno Kessler Foundation (fbk-irst, Amy L. Murphy, Prof Prabal Dutta, Prof Koen Langendoen, Prof Leo Selavo
"... April 29, 2011Für UnsShe had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it Lewis CarrollThe following document, written under the supervision of Dr. reviewed by: ..."
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April 29, 2011Für UnsShe had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it Lewis CarrollThe following document, written under the supervision of Dr. reviewed by:
Results 1 - 10 of 17