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Low Hardware Layered Decoding Architecture for LDPC Code

by N. Aravind, L. Praveen Kumar
"... Abstract: Low density parity check (LDPC) codes have been extensively adopted in next-generation forward error correction applications because they achieve very good performance using the iterative decoding approach of the belief-propagation (BP). The basic decoder design for achieving the highest d ..."
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directed towards achieving optimal tradeoffs between hardware complexity and decoding throughput. In particular, a time-multiplexed or folded approach, which is known as partially parallel decoder architecture, has been proposed. Low hardware layered decoding architecture for LDPC code scheme is proposed

Hardware Architecture for Modified Sequential LDPC Decoder

by Angus Wu, W. L. Lee, Tat Chee
"... Abstract:- Iterative decoding of Low Density Parity Check (LDPC) codes using the Parity Likelihood Ratio (PLR) algorithm have been proved to be more efficient compared to conventional Sum Product Algorithm (SPA). However, the nature of PLR algorithm tends to put numerious pieces of data to this deco ..."
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of quantization levels while still remaining the algorithmic performance promised by random codes. Moreover, a modified sequential architecture is proposed for LDPC decoding that decreases the decoding latency and reduces the memory storage compared to existing direct sequential design. Simulation results show

Low-power VLSI decoder architectures for LDPC codes

by Mohammad M Mansour , Naresh R Shanbhag - in Low Power Electronics and Design, 2002. ISLPED02. Proceedings of the 2002 International Symposium on , 2002
"... ABSTRACT Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximumlikelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major chall ..."
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ABSTRACT Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximumlikelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major

Joint ()-Regular LDPC Code and Decoder/Encoder Design

by Tong Zhang, Keshab K. Parhi
"... In the past few years, Gallager’s Low-Density Parity-Check (LDPC) codes have received a lot of attention and tremendous efforts have been devoted to analyze and improve their error-correcting performance. However, little consideration has been given to the practical LDPC codec hardware implementatio ..."
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performance but also exactly fit to a highspeed partly parallel decoder and low-complexity encoder. Moreover, we propose a modified joint design approach in order to further reduce the decoder hardware complexity for those high-rate ()-regular LDPC codes applied to silicon area critical applications

Unified decoder architecture for LDPC/Turbo codes

by Yang Sun, Joseph R. Cavallaro - in Proc. of the IEEE Workshop on Signal Processing Systems, (SiPS , 2008
"... Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code structures usually lead to different hardware implementations. In this paper, we propo ..."
Abstract - Cited by 7 (3 self) - Add to MetaCart
propose a unified decoder architecture that is capable of decoding both LDPC and turbo codes with a limited hardware overhead. We employ maximum a posteriori (MAP) algorithm as a bridge between LDPC and turbo codes. We represent LDPC codes as parallel concatenated single parity check (PCSPC) codes

A parallel decoding algorithm of LDPC codes using

by Shuang Wang, Samuel Cheng, Qiang Wu - CUDA”, Signals, Systems and Computers, 2008 42nd Asilomar Conference , 2008
"... Abstract—A parallel belief propagation algorithm for decoding low-density parity-check (LDPC) Codes is presented in this paper based on Compute Unified Device Architecture (CUDA). As a new hardware and software architecture for addressing and managing computations, CUDA offers parallel data computin ..."
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Abstract—A parallel belief propagation algorithm for decoding low-density parity-check (LDPC) Codes is presented in this paper based on Compute Unified Device Architecture (CUDA). As a new hardware and software architecture for addressing and managing computations, CUDA offers parallel data

Fully parallel stochastic LDPC decoders

by Saeed Sharifi Tehrani, Student Member, Shie Mannor, Warren J. Gross - IEEE Trans. on Signal Processing , 2008
"... Abstract—Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) de-coders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irr ..."
Abstract - Cited by 14 (1 self) - Add to MetaCart
Abstract—Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) de-coders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode

Scheduling Algorithm for Partially Parallel Architecture of LDPC Decoder by

by In-cheol Park, Se-hyeon Kang - Matrix Permutation,” IEEE International Conference on Circuits and Systems , 2005
"... Abstract — The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and complex interconnections. A practical solution of area-efficient decoders is to use the partially parallel archit ..."
Abstract - Cited by 9 (1 self) - Add to MetaCart
Abstract — The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and complex interconnections. A practical solution of area-efficient decoders is to use the partially parallel

FULLY PROGRAMMABLE LAYERED LDPC DECODER ARCHITECTURE

by Christiane Beuschel, Hans-jörg Pfleiderer
"... In this article we present a fully programmable layered LDPC decoder architecture together with an optimum mapping and scheduling algorithm. In contrast to other designs proposed in the literature, we use one-phase message passing. This allows for the first time the design of a fully programmable la ..."
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In this article we present a fully programmable layered LDPC decoder architecture together with an optimum mapping and scheduling algorithm. In contrast to other designs proposed in the literature, we use one-phase message passing. This allows for the first time the design of a fully programmable

Block-LDPC: A practical LDPC coding system design approach

by Hao Zhong, Student Member, Tong Zhang - IEEE Trans. Circuits Syst , 2005
"... Abstract—This paper presents a joint low-density parity-check (LDPC) code-encoder-decoder design approach, called Block-LDPC, for practical LDPC coding system implementations. The key idea is to construct LDPC codes subject to certain hardware-oriented constraints that ensure the effective encoder a ..."
Abstract - Cited by 35 (1 self) - Add to MetaCart
and decoder hardware implementations. We develop a set of hardware-oriented constraints, subject to which a semi-random approach is used to construct Block-LDPC codes with good error-correcting performance. Correspondingly, we develop an efficient encoding strategy and a pipelined partially par-allel Block-LDPC
Results 1 - 10 of 79