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23
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design
"... The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally acce ..."
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Cited by 1 (1 self)
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The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally
Analysis of System Bus Transaction Vulnerability Based on FMEA Methodology in SystemC TLM Design Platform
"... Abstract:- Intelligent safety-critical systems, such as intelligent automotive systems or intelligent robots, require a stringent reliability while the systems are in operation. As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting ..."
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more attention in the design industry while the SoC fabrication enters the very deep submicron technology. The system bus, such as AMBA AHB, provides an integrated platform for IP-based SoC. Apparently, the robustness of system bus plays an important role in the SoC reliability. In this study, we
IP Modeling and Reuse for SoC Design Using Standard Bus,” http:// www.us.design-reuse.com/articles/article4837.html
"... Most of system on chip (SoC) being designed today could reach several millions of gates and more than 2 GHz operating frequency. In order to implement such system, designers are increasingly relying on reuse of intellectual property (IP). In order to effectively re-use an IP in a system chip, a set ..."
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Cited by 1 (0 self)
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of abstracted models of the IP must be provided that enable the complete design and verification of the system chip that instantiates the IP. This work addresses the main issues in SoC design, namely the system design methodology, system level modelling, and IP integration for platform based design
Analysis of System Bus Transaction Vulnerability in SystemC TLM Design Platform
"... Abstract: As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. The system bus, such as AMBA AHB, provides an integrated plat ..."
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Cited by 1 (0 self)
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platform for IP-based SoC. Apparently, the robustness of system bus plays an important role in the SoC reliability. In this study, we propose a useful bus system vulnerability model and present a thorough analysis of system bus vulnerability in SystemC transaction-level modeling (TLM) design level
Communication Modeling for System-Level Design
"... Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate com ..."
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Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate
Using TLM for Exploring Bus-based SoC Communication Architectures
"... As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design requirements in shrinking time-to-market windows, and have begun using an IP-based SoC design methodology that permits r ..."
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Cited by 6 (0 self)
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Modeling (TLM) is an emerging abstraction that facilitates early exploration of SoC architectures. This paper outlines a typical IP-based SoC design flow, and presents the Cycle Count Accurate at Transaction Boundaries (CCATB) modeling abstraction which is a fast, efficient and flexible approach
Integration Methodology with Reusable & Configurable IPs Authors:
"... Ever wished a "plug-and-play " solution to build a subsystem & deliver it within a week!! Thanks to Synopsys Core * Solution & ST Microelectronics IP infrastructure, this is now possible. As travel options have evolved from "bullock-cart " era to Supersoni ..."
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. The methodology is implemented on Communication subsystem (COMMS) comprising of soft IP libraries based on the STBus architecture. The STBus bus architecture, designed & developed within STMicroelectronics, is used as a communication backbone for the subsystem & is able to support heavy pipelined data
Verifying External Interrupts of Embedded Microprocessor in SoC with on-chip bus
"... Abstract-The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. This paper proposes a aut ..."
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of the system complexity and can be easily migrated to different platforms/microprocessors. With little human effort, even an inexperience designer can generate extensive verification cases in a systematic way.
ARM-Based SoC Prototyping Platform Using Aptix
, 2005
"... ABSTRACT: With the consecutive progress in the process technology and state-of-the-art design methodology, multi-million gate-counts system-on-a-chip (SoC) design can be realistically fulfilled. However, the rapid prototyping verification and integration for SoC designs reveal a big challenge. In th ..."
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intellectual property (IP) designs from the public domain and academics, it is desired to shrink the integration time via a common platform. Thus, the proposed ARM-based SoC prototyping platform not only speeds up ARM-based SoC system verification using real hardware acceleration instead of the design sign
System-on-Chip Environment: A SpecC-based Framework for Heterogeneous MPSoC
- Design,”
, 2008
"... The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous syste ..."
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Cited by 37 (18 self)
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target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive
Results 1 - 10
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23
