### Table 11. The length of a test cube for each circuit is defined as the number of primary inputs and the number of flip-flops which together form the scan chain. The reduction factor in the last column of the table gives the ratio of the number of bits that we had to store without and with encoding of the test cubes:

### Table 6-3 Flip Flop Count in Reference Design

"... In PAGE 92: ... Tabl e6-2 presents a more detailed analysis of the data presented in Tabl e6-1. The first row in Table6 -2 repeats the prefix count for each database, the second row gives the total size of the table for each database. The third row gives the total number of bits stored for every bit of next hop pointer.... In PAGE 93: ... This analysis suggests that the ref- erence design and of Tree Bitmap is similar in storage to Lulea but without requiring a complete table compression to achieve the results. The final row of Table6 -2 gives the trie node savings by the use of path compression. On average 1 out of every 5 original trie nodes had only 1 extending path and no internal prefixes allowing it to be optimized out with path compression.... In PAGE 97: ...), an additional 250 flip flops are added to the tally. 250 Total 2640 Table6 -3 Flip Flop Count in Reference Design Block Function Flip Flop ... In PAGE 98: ....3.2. Design Summary For SRAM, the reference design has assumed a range of possible main memory sizes: 16k, 32k, 64k, 96k, and 128k nodes. Table6 -4 shows these 5 different memory sizes and for each presents the total table size, total design area (for SA-12 process), and the percent of an ASIC (144 mm 2 ) the design occupies. The final two columns first report the worst case number of prefixes supported with that table size based on the calculated ratio of 3.... In PAGE 98: ... With a 1.2 cm per side of die Table6 -4 SRAM Quantity effect on Die Area Size of Main Lookup Table (Number of Nodes) Size of Main Lookup Table in KBits a Total Area b (Square mm) Percent of ASIC for Main Memory c Worst Case Number of Prefixes Empirical Prediction for Number of Prefixes 16k 608 12.63 8.... ..."

### Table 6-3 Flip Flop Count in Reference Design

"... In PAGE 92: ... Tabl e6-2 presents a more detailed analysis of the data presented in Tabl e6-1. The first row in Table6 -2 repeats the prefix count for each database, the second row gives the total size of the table for each database. The third row gives the total number of bits stored for every bit of next hop pointer.... In PAGE 93: ... This analysis suggests that the ref- erence design and of Tree Bitmap is similar in storage to Lulea but without requiring a complete table compression to achieve the results. The final row of Table6 -2 gives the trie node savings by the use of path compression. On average 1 out of every 5 original trie nodes had only 1 extending path and no internal prefixes allowing it to be optimized out with path compression.... In PAGE 96: ... To estimate the number of register bits in the design it is necessary to review the various blocks in the design and call out the storage necessary for various functions as is done in Tabl e6-3. Table6 -3 Flip Flop Count in Reference Design Block Function Flip Flop Count Main Memory SRAM Interface For every Address and Data bit interfacing to the ram, the sig- nals need to be registered in this block {38*2 + 17}... In PAGE 98: ....3.2. Design Summary For SRAM, the reference design has assumed a range of possible main memory sizes: 16k, 32k, 64k, 96k, and 128k nodes. Table6 -4 shows these 5 different memory sizes and for each presents the total table size, total design area (for SA-12 process), and the percent of an ASIC (144 mm 2 ) the design occupies. The final two columns first report the worst case number of prefixes supported with that table size based on the calculated ratio of 3.... In PAGE 98: ... With a 1.2 cm per side of die Table6 -4 SRAM Quantity effect on Die Area Size of Main Lookup Table (Number of Nodes) Size of Main Lookup Table in KBits a Total Area b (Square mm) Percent of ASIC for Main Memory c Worst Case Number of Prefixes Empirical Prediction for Number of Prefixes 16k 608 12.63 8.... ..."

### TABLE V EFFECT OF THE NUMBER OF SCAN CHAINS ON SCAN/TOTAL FAULT COVERAGE AND WIRELENGTH FOR TESTCASE s38417 (FLOWS RAN WITHOUT DUMMY FLIP-FLOP INSERTION).

2003

### TABLE V EFFECT OF THE NUMBER OF SCAN CHAINS ON SCAN/TOTAL FAULT COVERAGE AND WIRELENGTH FOR TESTCASE s38417 (FLOWS RAN WITHOUT DUMMY FLIP-FLOP INSERTION).

2003

### Table 4 Flip-Flop SEU injection experimental results

"... In PAGE 6: ...Table 4 Flip-Flop SEU injection experimental results As seen from the numerical results in Table4 , VirtexDS scales extremely poorly with increasing number of simulated circuit execution cycles. It is evident that processor intensive simulation of a few thousands or tens of thousands clock cycles for large sequential circuits would be impractical.... ..."

### TABLE IV SCAN FAULT COVERAGE, CPLEX MIP NUMBER OF ITERATIONS, NUMBER OF BRANCH amp;BOUND NODES, AND RUNTIME FOR TESTCASE s38417 FOR VARYING NUMBER OF DUMMY FLIP-FLOPS.

2003

### TABLE IV SCAN FAULT COVERAGE, CPLEX MIP NUMBER OF ITERATIONS, NUMBER OF BRANCH amp;BOUND NODES, AND RUNTIME FOR TESTCASE s38417 FOR VARYING NUMBER OF DUMMY FLIP-FLOPS.

2003

### TABLE I THE TRUTH TABLE OF A 3X3 REVERSIBLE FUNCTION. flip-flop implementations based on this latch. We hope that this work will begin to fill the gap in this area of research.

### Table 3. The smallest Tc found, single-phase flip-flops, single-phase latches. (ns, nl: shortest amp; longest path delays of the balanced circuit.)

"... In PAGE 6: ...n any edge. The minimum pulse width of a clock is set to 1. First, we search for the smallest cycle time for which a solution can be found by basic and basic_r using single- phase latches and single-phase flip-flops. In Table3 , the number of inserted latches is listed both before merging fanout latches (nm) and after merging (m). Also shown are the new shortest and longest paths (ns, nl), the number of Table 1.... In PAGE 6: ... In Table 4, the ph column lists the total number of clock phases used in the solution. The numbers of latches (nm) in Table 4 before merging fanout latches are all smaller or equal to nm in Table3 (except for c1908), as are the numbers (m) after merging (except for c432 and c1355). This reduction is due to the general effectiveness of the heuristic algorithm in exploiting the relaxed insertion constraints of random-phase latches.... In PAGE 6: ... Third, we examine the smallest cycle time found by using random-phase latches and single-phase flip-flops (Table 5). The results show that the cycle times ( ) in Table 5 are smaller than or equal to in Table3 . This speedup also results from the relaxed constraints.... ..."