Results 1 - 10 of 154

A high-throughput VLSI architecture for deblocking filter

by Weiwei Shen, Qing Shang, Sha Shen, Yibo Fan, Xiaoyang Zeng - in HEVC,” in Proc. IEEE ISCAS , 2013
"... Abstract—As the next generation standard of video coding, the High Efficiency Video Coding (HEVC) aims to provide significantly improved compression performance in comparison with all existing video coding standards. We propose a four-stage pipeline hardware architecture on a quarter-LCU basis of de ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
of deblocking filter in HEVC. Coupled with the novel filter order, a memory interlacing technique is adopted to increase the throughput, which can access the data in the process of both vertical and horizontal filtering efficiently. As a result, our design can support 4Kx2K (4096x2048) at 30 fps applications

An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule

by Tsu-ming Liu, Wen-ping Lee, Chen-yi Lee - IEEE TRANS. CIRCUITS AND SYST. VIDEO TECHNOL , 2007
"... In this paper, we propose a high-throughput deblocking filter to perform the in-loop or post-loop filtering process for different standard requirements. The performance improvement is very mild if we replace a post-loop filter with an in-loop filter. To alleviate this problem, we derive an integrat ..."
Abstract - Cited by 7 (0 self) - Add to MetaCart
In this paper, we propose a high-throughput deblocking filter to perform the in-loop or post-loop filtering process for different standard requirements. The performance improvement is very mild if we replace a post-loop filter with an in-loop filter. To alleviate this problem, we derive

A memory-efficient deblocking filter for H.264/AVC video coding

by Tsu-ming Liu, Wen-ping Lee, Ting-an Lin, Chen-yi Lee - IEEE Int’l Symposium on Circuits and Systems , 2005
"... A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with s ..."
Abstract - Cited by 12 (1 self) - Add to MetaCart
A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared

A High-throughput, Area-efficient Hardware Accelerator for Adaptive Deblocking Filter in H.264/AVC

by Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir
"... Abstract—In this paper, we present a high-throughput, areaefficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard. In order to achieve this goal, we start with algorithmic optimization and propose a novel decomposition of the filter kernels for the deblockin ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
Abstract—In this paper, we present a high-throughput, areaefficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard. In order to achieve this goal, we start with algorithmic optimization and propose a novel decomposition of the filter kernels

A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter

by Yi-chih Chao, Ji-kun Lin, Jar-ferr Yang, Bin-da Liu
"... Abstract—In this paper, we propose a high throughput and data reuse architecture for de-blocking filter in H.264/AVC. There are two SRAMs exploited in the design. One is 144×32 bits single-port SRAM, and the other is 16×32 bits two-port SRAM. We use the group-of-pixel access method to store the pixe ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract—In this paper, we propose a high throughput and data reuse architecture for de-blocking filter in H.264/AVC. There are two SRAMs exploited in the design. One is 144×32 bits single-port SRAM, and the other is 16×32 bits two-port SRAM. We use the group-of-pixel access method to store

AN AREA-EFFICIENT AND HIGH-THROUGHPUT DE-BLOCKING FILTER FOR MULTI-STANDARD VIDEO APPLICATIONS

by Tsu-ming Liu, Wen-ping Lee, Chen-yi Lee
"... In this paper, we propose an area-efficient design approach to cover both in-loop and post-loop filtering processes for multiple video coding standards. In addition, we propose a hybrid filter scheduling to improve system throughput. Compared with available designs [1][2], the proposed approach save ..."
Abstract - Cited by 4 (1 self) - Add to MetaCart
In this paper, we propose an area-efficient design approach to cover both in-loop and post-loop filtering processes for multiple video coding standards. In addition, we propose a hybrid filter scheduling to improve system throughput. Compared with available designs [1][2], the proposed approach

A Novel Deblocking Filter Algorithm In H.264 for Real Time Implementation

by Yuan Li, Ning Han, Chen Chen
"... Abstract—Due to the limitation of computing complexity, it is difficult to apply the H.264 deblocking filter to low-end terminals. Although some technologies to optimize it have been proposed, the complexity is still high for real time implementation. Considering that deblocking filter is applied to ..."
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Abstract—Due to the limitation of computing complexity, it is difficult to apply the H.264 deblocking filter to low-end terminals. Although some technologies to optimize it have been proposed, the complexity is still high for real time implementation. Considering that deblocking filter is applied

3 Stage Pipelined Deblocking Filter for H.264/AVC

by Kyu-yeul Wang, Byung-soo Kim, Sang-seol Lee, Young-jun Kim, Bo-keun Choi, Duck-jin Chung , 2010
"... This paper describes the design and VLSI implementation of high throughput deblocking filter which adopted hybrid filtering order, single port memory, and hierarchical memory structure. The proposed deblocking filter used upper and left buffer. Because of this, the number of access to constructed p ..."
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This paper describes the design and VLSI implementation of high throughput deblocking filter which adopted hybrid filtering order, single port memory, and hierarchical memory structure. The proposed deblocking filter used upper and left buffer. Because of this, the number of access to constructed

High-Throughput Parallel Architecture for H.265/HEVC Deblocking Filter * HOAI-HUONG NGUYEN LE1 AND JONGWOO BAE1a)

by unknown authors
"... A novel parallel VLSI architecture is proposed in order to improve the performance of the H.265/HEVC deblocking filter. The overall computation is pipelined, and a new parallel-zigzag processing order is introduced to achieve high throughput. The pro-cessing order of the filter is efficiently rearra ..."
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A novel parallel VLSI architecture is proposed in order to improve the performance of the H.265/HEVC deblocking filter. The overall computation is pipelined, and a new parallel-zigzag processing order is introduced to achieve high throughput. The pro-cessing order of the filter is efficiently

A 136 CYCLES/MB, LUMA-CHROMA PARALLELIZED H.264/AVC DEBLOCKING FILTER FOR QFHD APPLICATIONS

by Jinjia Zhou, Dajiang Zhou, Hang Zhang, Yu Hong, Peilin Liu, Satoshi Goto
"... In this paper, we present a high-throughput deblocking filter archi-tecture for H.264/AVC in QFHD applications. In order to enhance the parallelism of filtering without notably increasing the area, we propose to parallelize the processing of luminance and chrominance samples, instead of simultaneous ..."
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In this paper, we present a high-throughput deblocking filter archi-tecture for H.264/AVC in QFHD applications. In order to enhance the parallelism of filtering without notably increasing the area, we propose to parallelize the processing of luminance and chrominance samples, instead
Results 1 - 10 of 154