Results 1 - 10 of 421

Cellular Automata Based Robust Watermarking Architecture towards the VLSI Realization

by V. H. Mankar, T. S. Das, S. K. Sarkar
"... Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI implement ..."
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Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI

Cellular Automata Based Robust Watermarking Architecture towards the VLSI Realization

by unknown authors
"... Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI implement ..."
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Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI

Efficient VLSI Architecture for ECG Data Compression

by Ruqaiya Khanam, Jamaia Millia, Syed Naseem Ahmad, Jamaia Millia Islamia
"... This paper presents an efficient ECG signals compression techniques using a 2D DWT coefficient thresholding and its design implementation of an efficient JPEG2000 encoder that employs the Distributed Arithmetic (DA) technique for the complex computation of Discrete Wavelet Transform (DWT).2D approac ..."
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computations, which can increase the speed and throughput as well. Architecture is based on the principles of pipelining and parallelism to obtain the optimal speed and throughput. Architecture is simple, modular and cascadable for computing a DA-DWT. This technique is faster when ROM table in on chip memory

VLSI Architecture of a Cellular Automata based One-Way Function

by D. Mukhopadhyay, P. Joshi, D. Roychowdhury
"... Abstract — In this paper, a technique to generate expander graphs using Cellular Automata (CA) has been presented. The special class of CA, known as the Two Predecessor Single Attractor Cellular Automata (TPSA CA) has been characterized. It has been shown that the expander graphs built using the TPS ..."
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Abstract — In this paper, a technique to generate expander graphs using Cellular Automata (CA) has been presented. The special class of CA, known as the Two Predecessor Single Attractor Cellular Automata (TPSA CA) has been characterized. It has been shown that the expander graphs built using

A Parallel Architecture for High Speed Data Compression

by James Storer Computer , 1991
"... Data compression is becoming an essential component of high speed data communications and storage. Lossless data compression is when the decompressed data must be identical to the original. Textual substitution methods are among the most powerful approaches to lossless data compression, where repeat ..."
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that can "learn" new strings based on the text processed thus far. Key to the design of this architecture is the formulation of an inherently "top-down" serial learning strategy as a "bottom up" parallel strategy. A custom VLSI chip for this architecture that operates at 300

International Journal of Electrical and Computer Engineering 2:3 2007 Cellular Automata Based Robust Watermarking Architecture towards the VLSI Realization

by V. H. Mankar, T. S. Das, S. K. Sarkar
"... Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI implement ..."
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Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI

Programmable Parallel Arithmetic Cellular Automata using a Particle Model

by Richard K. Squier, Ken Steiglitz , 1994
"... In this paper we show how to embed practical computation in onedimensional cellular automata using a model of computation based on collisions of moving particles. The cellular automata have small neighborhoods, and state spaces which are binary occupancy vectors. They can be fabricated in VLSI, and ..."
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In this paper we show how to embed practical computation in onedimensional cellular automata using a model of computation based on collisions of moving particles. The cellular automata have small neighborhoods, and state spaces which are binary occupancy vectors. They can be fabricated in VLSI

Cam-8: a computer architecture based on cellular automata

by Norman Margolus - Proceedings of the Pattern Formation and Lattice-Gas Automata Conference. Fields Institute, American Mathematical Society , 1993
"... The maximum computational density allowed by the laws of physics is available only in a format that mimics the basic spatial locality of physical law. Fine-grained uniform computations with this kind of local interconnectivity (Cellular Automata) are particularly good candidates for efficient and ma ..."
Abstract - Cited by 41 (8 self) - Add to MetaCart
The maximum computational density allowed by the laws of physics is available only in a format that mimics the basic spatial locality of physical law. Fine-grained uniform computations with this kind of local interconnectivity (Cellular Automata) are particularly good candidates for efficient

Efficient VLSI for Lempel-Ziv Data Compression in Wireless Data Communication Networks

by Bongjin Jung, Wayne P. Burleson
"... We present a parallel algorithm, architecture, and implementation for efficient Lempel-Ziv-based data compression. The parallel algorithm exhibits a scalable, parameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design ..."
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We present a parallel algorithm, architecture, and implementation for efficient Lempel-Ziv-based data compression. The parallel algorithm exhibits a scalable, parameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design

Architectural advances in the VLSI implementation of arithmetic coding for binary image compression

by Gennady Feygin, Patrick Glenn Gulak, Paul Chow - National Taiwan University , 1994
"... This paper presents some recent advances in the architecture for the data compression technique known as Arithmetic Coding. The new architecture em-ploys loop unrolling and speculative execution of the inner loop of the algorithm to achieve a significant speed-up relative to the Q-Coder architecture ..."
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ever been published. For the CCITT facsimile documents, the new architecture achieves a speed-up of approximately seven compared to the IBM Q-coder when four lookahead units are employed in parallel. A structure for fast Input/Output processing based on run length pre-coding of the data stream
Results 1 - 10 of 421