Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software

cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among

. We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples from the DIMACS benchmark suite, high raw speed-ups over software can be achieved. We present a design tool flow and prototype

Abstract—A modular design is proposed and analyzed for accelerating the publish/subscribe matching algorithm in reconfigurable hardware. With help from a performance model, we demonstrate an optimized FPGA implementation which is scalable and efficient enough for many of today’s most demanding web

a hardware accelerator and a 16-bit MAC-PHY interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator. Architecture, design, implementation, and test of a reconfigurable digital baseband processor are described too. Description includes the baseband

that automatically compiles system-level applications specified in C to executables on the target platform. A key component of this framework is a hardware/software partitioning algorithm that performs finegrained partitioning (at loop and basic-block levels) of an application to execute on the combined CPU

features. The concept of Reconfigurable computing allows the acceleration of computational processes by using variable configurations of specialized hardware. The FPGAs are opening a new door in digital processing environments by providing Reconfigurability at different granularity levels. Further

and flexible usage of TPM functionalities. In this paper we propose a reconfigurable (hardware) architecture with TC functionalities where we focus on TPMs as proposed by the TCG specifically designed for embedded platforms. Our approach allows for (i) an efficient and scalable design and update of TPM

Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., Cell/BE SPUs) or data-parallel accelerators (e.g., GPGPUs). Approaching the theoretical performance

in an automated manner is highly desired. In this paper, we describe TANOR an automated tool targeted for designing hardware accelerators for the class of N-body interaction problems. The design flow, starting from a high level (MATLAB) description, configures the entire system automatically. We describe