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Reconfigurable Computing: A Survey of Systems and Software

by Katherine Compton, Scott Hauck , 2000
"... Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solu ..."
Abstract - Cited by 258 (5 self) - Add to MetaCart
Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software

2011 21st International Conference on Field Programmable Logic and Applications A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

by Juan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza
"... Abstract — Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware c ..."
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cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among

Acceleration of Satisfiability Algorithms by Reconfigurable Hardware

by Marco Platzner, Giovanni De Micheli - In International Workshop on Field-Programmable Logic and Applications (FPL , 1998
"... . We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples from the DIMACS benchmark suite, high raw speed-ups over software can be achieved. We present a design tool flow and prototype ..."
Abstract - Cited by 18 (3 self) - Add to MetaCart
. We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples from the DIMACS benchmark suite, high raw speed-ups over software can be achieved. We present a design tool flow and prototype

Accelerating Publish/Subscribe Matching on Reconfigurable Supercomputing Platform

by K. H. Tsoi, I. Papagiannis, M. Migliavacca, W. Luk, P. Pietzuch
"... Abstract—A modular design is proposed and analyzed for accelerating the publish/subscribe matching algorithm in reconfigurable hardware. With help from a performance model, we demonstrate an optimized FPGA implementation which is scalable and efficient enough for many of today’s most demanding web a ..."
Abstract - Cited by 4 (0 self) - Add to MetaCart
Abstract—A modular design is proposed and analyzed for accelerating the publish/subscribe matching algorithm in reconfigurable hardware. With help from a performance model, we demonstrate an optimized FPGA implementation which is scalable and efficient enough for many of today’s most demanding web

MAC and Baseband Hardware Platforms

by unknown authors
"... Abstract — The paper describes hardware solutions for the IEEE 802.11 MAC (Medium Access Control) layer and IEEE 802.11a digital baseband in an RF-MIMO WLAN transceiver that performs the signal combining in the analogue domain. Architecture and implementation details of the MAC processor including a ..."
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a hardware accelerator and a 16-bit MAC-PHY interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator. Architecture, design, implementation, and test of a reconfigurable digital baseband processor are described too. Description includes the baseband

Hardware-Software Co-Design of Embedded Reconfigurable Architectures

by Yanbing Li, Tim Callahan, Ervan Darnell, Randolph Harr, Uday Kurkure, Jon Stockwood , 2000
"... In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and a memory hierarchy. We have developed a framework called Nimble that automatica ..."
Abstract - Cited by 83 (2 self) - Add to MetaCart
that automatically compiles system-level applications specified in C to executables on the target platform. A key component of this framework is a hardware/software partitioning algorithm that performs finegrained partitioning (at loop and basic-block levels) of an application to execute on the combined CPU

Reconfiguration

by M. S. Karpe, A. M. Lalge, S. U. Bh
"... The term ’Software Radio ’ was coined by Joseph Mitola III to signal the shift from HW design dominated radio systems to systems where the major part of the functionality is defined in software. It creates a necessity of generic programmable hardware base that would allow software to enable various ..."
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features. The concept of Reconfigurable computing allows the acceleration of computational processes by using variable configurations of specialized hardware. The FPGAs are opening a new door in digital processing environments by providing Reconfigurability at different granularity levels. Further

Reconfigurable Trusted Computing in Hardware

by Thomas Eisenbarth, Tim Güneysu, Christof Paar - In ACM STC ’07
"... Trusted Computing (TC) is an emerging technology towards building trustworthy computing platforms. The Trusted Computing Group (TCG) has proposed several specifications to implement TC functionalities by extensions to common computing platforms, particularly the underlying hardware with a Trusted Pl ..."
Abstract - Cited by 16 (2 self) - Add to MetaCart
and flexible usage of TPM functionalities. In this paper we propose a reconfigurable (hardware) architecture with TC functionalities where we focus on TPMs as proposed by the TCG specifically designed for embedded platforms. Our approach allows for (i) an efficient and scalable design and update of TPM

Starpu: a unified platform for task scheduling on heterogeneous multicore architectures,

by Cédric Augonnet , Samuel Thibault , Raymond Namyst , Pierre-André Wacrenier - Concurrency and Computation: Practice and Experience , 2011
"... Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., Cell/BE SPUs) or data-parallel accelerators (e.g., GPGPUs). Approaching the theoretical performance of these architectu ..."
Abstract - Cited by 172 (15 self) - Add to MetaCart
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., Cell/BE SPUs) or data-parallel accelerators (e.g., GPGPUs). Approaching the theoretical performance

TANOR: A Tool for Accelerating N-body Simulations on Reconfigurable Platform

by J. S. Kim, P. Mangalagiri, K. Irick, V. Narayanan, K. Sobti, L. Deng, C. Chakrabarti
"... Algorithm-architecture co-exploration is hindered by the lack of efficient tools. As a consequence, designers are currently able to explore only a limited set of points in the whole design space. Therefore, a tool that can allow fast exploration of algorithmic and architectural tradeoffs in an autom ..."
Abstract - Cited by 6 (2 self) - Add to MetaCart
in an automated manner is highly desired. In this paper, we describe TANOR an automated tool targeted for designing hardware accelerators for the class of N-body interaction problems. The design flow, starting from a high level (MATLAB) description, configures the entire system automatically. We describe
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