describe MPICH, unique among existing implementations in its design goal of combining portability with high performance. We document its portability and performance and describe the architecture by which these features are simultaneously achieved. We also discuss the set of tools that accompany the free

Abstract—We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually

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This paper presents an architectural power estimation tool that can accurately estimate the power consumptions of analog-to-digital converters. Combining the advantages of both the bottom-up approach and the top-down approach, the estimator can help AMS SoC designer on high level power optimized

Following published procedures for characterizing ADCs using phase-plane error functions, this paper shows how a given calibration data set may used to extract estimates of specific error performance features pertaining to ADC architectural considerations. The procedure requires the selection

A calibration procedure for analog-to-digital converters working purely in the digital domain is presented. The proposed method is based on a linear-filter reconstruction of an analog calibration signal. The reconstructed version of the calibration signal is employed in designing an updated

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Abstract: Parallel database machine architectures have evolved from the use of exotic hardware to a software parallel dataflow architecture based on conventional shared-nothing hardware. These new designs provide impressive speedup and scaleup when processing relational database queries. This paper

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