• Documents
  • Authors
  • Tables
  • Log in
  • Sign up
  • MetaCart
  • DMCA
  • Donate

CiteSeerX logo

Tools

Sorted by:
Try your query at:
Semantic Scholar Scholar Academic
Google Bing DBLP
Results 1 - 10 of 37,068
Next 10 →

Low-Power CMOS Digital Design

by Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen - JOURNAL OF SOLID-STATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413 , 1992
"... Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the ..."
Abstract - Cited by 570 (20 self) - Add to MetaCart
the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved

Wattch: A Framework for Architectural-Level Power Analysis and Optimizations

by David Brooks, Vivek Tiwari, Margaret Martonosi - In Proceedings of the 27th Annual International Symposium on Computer Architecture , 2000
"... Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high ..."
Abstract - Cited by 1295 (43 self) - Add to MetaCart
Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve

Wireless sensor networks: a survey

by I. F. Akyildiz, W. Su, Y. Sankarasubramaniam, E. Cayirci , 2002
"... This paper describes the concept of sensor networks which has been made viable by the convergence of microelectro-mechanical systems technology, wireless communications and digital electronics. First, the sensing tasks and the potential sensor networks applications are explored, and a review of fact ..."
Abstract - Cited by 1936 (23 self) - Add to MetaCart
This paper describes the concept of sensor networks which has been made viable by the convergence of microelectro-mechanical systems technology, wireless communications and digital electronics. First, the sensing tasks and the potential sensor networks applications are explored, and a review

Wrapper Induction for Information Extraction

by Nicholas Kushmerick , 1997
"... The Internet presents numerous sources of useful information---telephone directories, product catalogs, stock quotes, weather forecasts, etc. Recently, many systems have been built that automatically gather and manipulate such information on a user's behalf. However, these resources are usually ..."
Abstract - Cited by 612 (30 self) - Add to MetaCart
are usually formatted for use by people (e.g., the relevant content is embedded in HTML pages), so extracting their content is difficult. Wrappers are often used for this purpose. A wrapper is a procedure for extracting a particular resource's content. Unfortunately, hand-coding wrappers is tedious. We

The Future of Wires

by Mark Horowitz, Ron Ho, Ken Mai , 1999
"... this paper we first discuss the wire metrics of interest and examine them in a contemporary 0.25m process. We then discuss technology scaling over the next several generations, from SIA and other predictions, and how our wire metrics trend over that time. We will examine the delay and bandwidth lim ..."
Abstract - Cited by 508 (7 self) - Add to MetaCart
this paper we first discuss the wire metrics of interest and examine them in a contemporary 0.25m process. We then discuss technology scaling over the next several generations, from SIA and other predictions, and how our wire metrics trend over that time. We will examine the delay and bandwidth

Wireless Communications

by Andrea Goldsmith, Anaïs Nin , 2005
"... Copyright c ○ 2005 by Cambridge University Press. This material is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written permission of Cambridge University ..."
Abstract - Cited by 1129 (32 self) - Add to MetaCart
Copyright c ○ 2005 by Cambridge University Press. This material is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written permission of Cambridge University

The Landscape of Parallel Computing Research: A View from Berkeley

by Krste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams, Katherine A. Yelick - TECHNICAL REPORT, UC BERKELEY , 2006
"... ..."
Abstract - Cited by 468 (25 self) - Add to MetaCart
Abstract not found

CMOS Voltage Reference

by Chun-yu Hsieh, Hong-wei Huang, Ke-horng Chen, Senior Member
"... Abstract—An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35- m CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V-type transistors to operat ..."
Abstract - Add to MetaCart
Abstract—An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35- m CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V-type transistors

CMOS

by Purdue E-pubs, Ik Joon Chang, Ik Joon Chang, Jae-joon Kim, Sang Phill Park, Kaushik Roy , 2008
"... A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS ..."
Abstract - Add to MetaCart
A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS

High-performance poly-Si nanowire NMOS transistors

by Horng-chih Lin, Senior Member, Chun-jung Su, Student Member - IEEE Trans. Nanotechnol , 2007
"... Abstract—A novel field-effect transistor with Si nanowire (NW) channels is developed and characterized. To enhance the film crystallinity, metal-induced lateral crystallization (MILC) and/or rapid thermal annealing (RTA) techniques are adopted in the fabrication. In the implementation of MILC proces ..."
Abstract - Cited by 5 (2 self) - Add to MetaCart
Abstract—A novel field-effect transistor with Si nanowire (NW) channels is developed and characterized. To enhance the film crystallinity, metal-induced lateral crystallization (MILC) and/or rapid thermal annealing (RTA) techniques are adopted in the fabrication. In the implementation of MILC
Next 10 →
Results 1 - 10 of 37,068
Powered by: Apache Solr
  • About CiteSeerX
  • Submit and Index Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2019 The Pennsylvania State University