. (2007). A Ka band, static, MCML frequency divider, in standard 90nm-CMOS LP for 60 GHz applications. In IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 : 3 -5 June 2007 Please check the document version of this publication: • A submitted manuscript is the version of the article

architecture with RF phase-shifting is proposed and design, analysis and measurements of its key components are presented. A high-gain, two-stage, low noise amplifier in 90 nm-CMOS technology with more than 20 dB gain over the 60 GHz spectrum is designed. Furthermore, a broadband analog phase shifter with a

This paper presents key design techniques and challenges in implementing one of the first integrated, energy-efficient 60GHz transceivers including baseband circuitry. The 90nm CMOS direct-conversion design (Fig. 18.5.1) operates from a 1.2V supply and has been optimized for 5-to-10Gb/s QPSK

Emerging applications for the 60GHz spectrum include extremely high-data-rate short-range communication systems. Many of these applications are expected to enter the realm of consumer electronics where low cost and mass production are prerequisites, favoring the application of digital CMOS

(LNA) with a 12.5 dB peak gain and a 5.4 dB minimum NF is demonstrated in a 90 nm CMOS technology. The LNA is com-posed of four cascaded common-source stages with the gate-source transformer feedback applied to the input stage for simultaneous noise and input matching. Also, the drain

designed and fabricated. The amplifier has a measured power gain of 9.8 dB. The input is gain matched while the output is matched to maximize the output power. The measured P−1dB = 6.7 dBm with a corresponding power added efficiency of 20%. This amplifier can be used as a pre-driver or as the main

Recently, 7GHz of unlicensed bandwidth around 60GHz was opened allowing for a variety of applications including Gb/s point-to-point links, wireless local area networks with extraordinary capacity, and vehicular radar at nearby frequencies. Presently, the exploitation of this band is minimal because

. Furthermore, most of the mm-wave PAs reported use bulky transmission lines [2, 3], increasing silicon area and incurring higher substrate losses. We demonstrate a fully integrated 60GHz transformer-coupled two-stage differential power amplifier with single-ended input and output in 90nm digital CMOS

This paper presents experimental measurements of the dif-ferences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better in-formed choices

fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency (RF) of 60 GHz, intermediate frequency (IF) of 2 GHz, and low LO power of 0 dBm, conversion loss is better than 2 dB, and an input-referred 1-dB compression point of – 3.5 dBm was measured