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197
A 3D SoC design for H.264 application with on-chip DRAM stacking
- In 3D Systems Integration Conference (3DIC), 2010 IEEE International
, 2010
"... Abstract-Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the "memory wall" challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to commun ..."
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Cited by 2 (0 self)
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) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint of I/O pin count. To demonstrate the feasibility of 3D memory stacking, this paper introduces a 3D System-on-Chip (SoC) for H.264 applications that can make use of multiple
Leveraging On-chip DRAM Stacking in an Embedded 3D Multi-Core DSP System
"... Abstract-Embedded multi-core systems are gaining popularity for many embedded applications. Compared to the multicore design for general purpose high performance computing, the memory design for an embedded multi-core processor should be customized and adapt to embedded application's character ..."
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's characteristics, because it usually has significant impact on the system performance. In this paper, we study a 3D embedded multi-core DSP processor called 3D-iSPA, which is targeted for multimedia applications with two unique design features and leverages 3D DRAM stacking to improve performance. Many memory
An On-Chip Interconnect and Protocol Stack for Multiple Communication Paradigms and Programming Models
- CODES+ISSS'09
, 2009
"... A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication parad ..."
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Cited by 13 (4 self)
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A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication
A multi-layered on-chip interconnect router architecture
- in Proceedings of the 35th International Symposium on Computer Architecture
, 2008
"... Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has em ..."
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Cited by 21 (0 self)
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Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has
25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM
"... Abstract—In this paper we introduce a 14-core application processor for multimedia mobile applications, implemented in 40 nm, with a 222 mW H.264 full high-definition (full-HD) video engine, a 124 mW 40 M-polygons/s 3D/2D graphics engine, and a video/audio multiprocessor for various Codecs and image ..."
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, the Stacked Chip SoC (SCS) technology enables rewiring to the DRAM chip during assembly/packaging phase using a wire with 10 m minimum pitch on Re-Distribution Layer (RDL) using electroplating. The peak memory bandwidth is 10.6 GB/s with an x512b SCS-DRAM interface, and the power consumption of this interface
Throughput-Effective On-Chip Networks for Manycore Accelerators
, 2010
"... Abstract—As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnec-tion network design. This paper explores throughput-effective network-on-chips (NoC) for future manycore accelerators that emp ..."
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Cited by 11 (0 self)
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Abstract—As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnec-tion network design. This paper explores throughput-effective network-on-chips (NoC) for future manycore accelerators
A Design Methodology for Application-Specific Networks-on-Chip
- ACM Transactions on Embedded Computing Systems
, 2006
"... With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodol ..."
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Cited by 20 (6 self)
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With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign
An rdlconfigurable 3d memory tier to replace on-chip sram
- in Design, Automation Test in Europe Conference Exhibition (DATE
, 2010
"... Abstract—In a conventional SoC designs, on-chip memories occupy more than the 50 % of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system des ..."
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Cited by 1 (0 self)
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Abstract—In a conventional SoC designs, on-chip memories occupy more than the 50 % of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system
Unison cache: A scalable and effective die-stacked dram cache
- in Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on, Dec 2014
"... Abstract—Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of off-chip bandwidth. Today’s stacked ..."
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Cited by 1 (0 self)
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a page. In doing so, the Footprint Cache achieves high hit rates with moderate on-chip tag storage and reasonable lookup latency. However, multi-gigabyte stacked DRAM caches will soon be practical and needed by server applications, thereby mandating tens of MBs of tag storage even for page
Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache
"... AbstractTechnology scaling is increasingly yielding diminish-ing returns in terms of product performance, power, and its yield. Recent development in through-silicon via (TSV) technology has made multi-layer stacking (or 3D integration) a viable solution, opening possibility for coping with the issu ..."
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remains as a challenge in realizing large on-chip memories. Heterogeneous 3D integration has been widely adopted for bringing analog, RF, MEMS, DRAM, SRAM, among other wide application on a single chip. In this work, we propose to use heterogeneous 3D integration as an alternative means to manufacture
Results 1 - 10
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197
