### Table 1. FFT Power Comparison

"... In PAGE 4: ... The power consumption of the fabricated FFT-4 and completed implementation of the FFT-16 has been used to estimate the overall power efficiency of a 1024-point FFT. These results are shown in comparison with other FFT designs in Table1 . In addition to these reductions in power consumption, we achieved a remarkably high sustained throughput as can be observed in Table 2.... ..."

### Table 2: FFT Performance Comparison

"... In PAGE 3: ...shown in comparison with other FFT designs in Table 1. In addition to these reductions in power consumption, we achieved a remarkably high sustained throughput as can be observed in Table2 . All designs are measured using a 3.... ..."

### (Table 1). Those rates show that at full stream speed not all the mappings are compliant with the physical layer Hiperlan/2 specification, which requires a bit rate in excess of 12 Mbit/sec. However, each one shows different characteristics that may make it more or less desirable for other application families, such as low bit rate not-standard radio. For instance, the scenarios involving the fastest FFT architecture result in the highest bit rate at the price of a larger area and power consumption estimate. The system model today provides only latency/throughput information, but the architectural services could be extended to provide also area and activity (power) information.

2003

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### Table 5.8: Performance comparison of 64-point FFT pipeline for high speed Architecture Gate Count Critical Power (mW)

2001

### Table 2: Summary The table shows, for both the radix-4 and the radix- 8 dividers, a reduction in the energy-per-division of about 40% in the low-power implementation. An im- plementation with dual voltage will show a reduction of about 70% for both radices. The speed-up for the radix-8 over the radix-4 is about 17%, while the in- crease in the energy-per-division is less than 2% in the low-power implementation. In the dual voltage im- plementation, our estimate indicates that the energy-

"... In PAGE 6: ...0 nJ, corresponding to a reduction of 70%. 6 Comparison between the Radix-4 and the Radix-8 Divider Table2 summarizes the characteristics of the two di- viders. The energy-per-division is split in the contri- bution of the recurrence and that of the conversion and rounding.... ..."

### Table 1: Truth table for radix-4 modifled Booth recoding.

2005

"... In PAGE 9: ... Goto et al. showed that the area of the Booth selector highly depends on the encoding of the radix-4 digits [5] and proposed a solution with four bits ( Table1 a): PLi (positive), Mi (negative), 2Ri (doubled factor), and Ri (unchanged factor). Table 1b describes the computation of these control signals from two digits of a radix-2 RN-coding X.... In PAGE 9: ... showed that the area of the Booth selector highly depends on the encoding of the radix-4 digits [5] and proposed a solution with four bits (Table 1a): PLi (positive), Mi (negative), 2Ri (doubled factor), and Ri (unchanged factor). Table1 b describes the computation of these control signals from two digits of a radix-2 RN-coding X. Note that several patterns never occur (we denote them by `).... ..."

### Table 3 Test Set low low high high

"... In PAGE 12: ... With this network architecture we obtained a maximal correlation coefficient of 0.42, corresponding to finding 67% of the glycosylated threonines and 88% of the non-glycosylated threonines in the low similarity test set ( Table3 ). On this novel test set the matrix method of Elhammer et al.... In PAGE 13: ...orrelation coefficient. However, a window of 39 residues was nearly as good. This indicates the existence of correlations between distant residues in the sequence, and reaffirms that the acceptor sequence pattern for serine differs from that of threonine. Table3 reports the performance values (C, percentages of correctly predicted glycosylated residues and non-glycosylated residues) on the low similarity test set: 0.33, 60%, 97%, respectively.... ..."

### Table 3. IIR Throughput Comparison Architecture

"... In PAGE 6: ... We also see here that the FPGA FIRs are 30 more dense than the DSPs, underscoring the reason for the high interest in FPGAs for this application. IIR Table3 contains a similar comparison for biquads, the core computation for In nite Impulse Response (IIR) computations. Here the multipliers cannot be specialized around the coe cient, so the FPGA su ers a full 50 density penalty versus a programmable, custom IC for IIR.... ..."

### Table 1: Comparison of hardware cost and power consumption of the logarithmic low-power DCT architecture with other approaches.

1995

"... In PAGE 6: ...5 frequency at the nal stage, we need a total of (log M +2) multipliers to realize the multirate transfer function. The comparison of the logarithmic low-power architecture with other approaches is listed in Table1 . Although the total power savings of the logarithmic structure is less than that of the full multirate structure given the same decimation factor M, the O(log M) hardware overhead is preferable when we want to achieve low-power consumption without trading too much chip area.... ..."

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