### Table 1: Exchange Algorithms for Equiripple Filters

1995

"... In PAGE 2: ... The corresponding design of multiband lters requires more care however [22]. Table1 classi es four approaches. We note, however, that the Shpak-Antoniou algorithm, when applied to multiband lter design, achieves a number of extra ripples speci ed by the user.... ..."

Cited by 1

### Table 2: Experimental results for FIR Filter

"... In PAGE 3: ... It accepts one input, produces one output and contains 17 multiplications and 16 additions. Table2 shows the results for the non-CED design and CED design using allocation diversity, idle cycles and the semi CED in column 2, 3, 4 and 5 respectively. The second and third rows show the number of operators used by these designs.... In PAGE 4: ... Table 3 shows the results for all designs. The meaning of each row is same as in Table2 . The non-CED design uses four adders, four multipliers and takes 11 clock cycles.... ..."

### Table 3: 10,240-tap FIR filter design statistics

"... In PAGE 8: ... Each FPGA implements 512 taps, and all 20 FPGAs aggregate to 10240 taps. Figure 9: A single FIR tap implementation As summarized in Table3 , this benchmark FIR design illustrates that each BPU is capable of operating at full capacity with a throughput of up to 600 billion operations per second, while emulating an 8 million ASIC gate equivalent design. Since the FIR design does not utilize any of the on-chip dedicated 640 Kbit RAM components, the total capacity upper bound including memory is at least 10 million gates per BPU.... ..."

### Table 1. Comparison of code sizes for the FIR-filter designs

1998

"... In PAGE 6: ...y an enable signal from the sum unit. The third model is the fully synchronous model. It runs at half the clock speed as the other two, since it does not have any Clock Protocol that need to derive an internal clock from a faster, external, one like the other two protocols need. The number of ProGram lines of code and the number of VHDL lines of code needed to describe in the FIR-filter designs we are using our case study, are shown in Table1 . As can be seen, the ratio is around 6 times less, which means that the final design should have 6 times less bugs if the number of bugs per lines are the same for both languages.... ..."

Cited by 2

### Table 1: The implementation load per recursion for adaptive Laguerre and FIR filter with the NLMS algorithm.

"... In PAGE 3: ... The parameters estimate a15 a64 a1a10a3a6a5 is defined as the minimum of the mean-squared error criterion: a15 a64 a1a10a3a6a5a143a11a109a123a12a124a41a125a143a126a116a127a28a128 a129a183a182 a117 a16 a1a4a3a6a5 a73 a119 (22) which is solved using the NLMS algorithm: a15 a64 a1a10a3a6a5a143a11 a15 a64 a1a4a3a2a44a173a65a115a5a81a13 a148 a184 a105a138a1a4a3a39a38a59a79a43a5 a184 a73 a105a138a1a10a3a39a38a41a79a2a5 a16 a1a4a3a6a5 (23) where a148 is a gain and the a priori error is a16 a1a4a3a6a5a17a11 a9 a1a4a3a6a5a12a44 a15 a9 a1a4a3a6a5 . Table1 compares the computational complexity required to implement adaptive filters which use the Laguerre and FIR filter as the filter structures, and the NLMS algorithm as the adaptation algorithm. The ratio of complexity required by the adaptive Laguerre filter to the one required by the adaptive FIR filter is only about 1.... ..."

### TABLE I The Chebyshev window function and corresponding narrown2dband FIR filter based on the Zolotarev polynomial

### Table 2. Number of operations for N-tap FIR filter.

1997

"... In PAGE 9: ...Journal of VLSI Signal Processing KL534-Verbauwhede February 14, 1998 8:59 A Low Power DSP Engine for Wireless Communications 185 in this architecture are in the reduction of the memory accesses as is summarized in Table2 . The total number of multiplications remains the same whether they are executed on one MAC, a DUAL MAC or an N-MAC architecture because the energy for the multiplications is a fundamental need.... ..."

### Table 2: Number of Operations for N-tap FIR Filter.

1997

"... In PAGE 23: ... The overhead sits in the instruction fetching, decoding, memory accesses, and other logic. The main energy savings in this architecture are in the reduction of the memory accesses as is summarized in Table2 . The total number of multiplications remains the same whether they are executed on one MAC, a DUAL MAC or an N-MAC architecture because the energy for the multiplications is a fundamental need.... ..."

### Table 2: Complexity in terms of amount of information exchanged or operations performed for each phase of the computation.

1999

"... In PAGE 19: ... Remember that a word copy requires two word accesses: a read and a write access. Table2 summarizes the complexity of each one of the algorithm phases. The complexity listed in Table 2 is for a single execution of the phase.... In PAGE 19: ... Table 2 summarizes the complexity of each one of the algorithm phases. The complexity listed in Table2 is for a single execution of the phase. To obtain the portion of time spent in each phase we also need to take into consideration the hardware speed, the number of times that each phase has to be performed, and the overlapping among phases.... In PAGE 20: ...Table 3: Hardware parameters assumed for the design point for the year 2006/2007 6 Hardware Parameters To estimate how long a sub-block multiplication in a SPELL takes, we have to multiply the number of oating point operations given in Table2 by the average period of a SPELL oating point unit and divide by the number of units available in the SPELL: MS = 2 (bc)3 SFt #F P U=SP ELL (10) where MS is the average time required for one sub-block multiplication, and SFt is the average cycle of the SPELL FPU. A SPELL processor has 5 oating-point functional units (FPUs) operating with an average cycle time, SFt, of about 15 ps [8] 4.... In PAGE 22: ... If we assume that MS gt; DS, Dt[A] = Dt[B], IPDS = OPSD, and IPSC = OPCS, we can rewrite equations 16 and 17 as T = 2 Dt[A] + 3 IPDS + t2 TB + Dt[C] (18) TB = t s MS + (2t + 1) IPSC (19) replacing equation 19 in equation 18 we obtain T = 2 Dt[A] + Dt[C] + 3 IPDS + t3 s MS + t2 (2t + 1) IPSC (20) We now want to estimate each one of the components of the execution time. Table2 has the expression for the number of word accesses required for the transformation of matrices A, B and C in DRAM. The data transformation in DRAM is performed in parallel by s2 DPIMs.... ..."

Cited by 3

### Table 1: Filter weights obtained by the adaptive algorithms.

"... In PAGE 19: ... The desired signal d(n) was obtained by passing s(n) through an FIR lowpass lter of window length N = 11, designed for a cuto frequency !c = 50. The weights of the designed lter are shown in Table1 , in the column entitled `Lowpass FIR apos;. Fig.... In PAGE 21: ... The step-sizes for the linear lter ( = 1:0 10?4) and the weighted median lter ( = 5:0 10?3) were chosen so that these algorithms converged in approximately the same number of iterations as the fastest weighted myriad lter algorithm (which was Algorithm II). The nal lter weights obtained by the various algorithms are shown in Table1 . The three weighted myriad lter algorithms converged to approximately the same weight vectors.... ..."