Results 1 - 10 of 299,956

Table 1. Evaluation of the Initial Mapping and Scheduling

in Scheduling and Mapping in an Incremental Design Methodology for Distributed Real-Time Embedded Systems
by Paul Pop, et al.
"... In PAGE 14: ... In our experiments we compared the quality of designs (in terms of schedule length) produced by IMS with those generated with the original HCP algorithm proposed in [13]. Results are de- picted in Table1 where we have three columns for both HCP and IMS. In the columns labelled average we present the av- erage percentage deviations of the schedule length produced with HCP and IMS from the length of the best schedule among the two.... ..."

Table 2: Hardware Platforms

in Analyzing and Modeling Encryption Overhead For Sensor Network Nodes
by Prasanth Ganesan, Ramnath Venugopalan, Pushkin Peddabachagari, Alexander Dean, Frank Mueller, Mihail Sichitiu 2003
"... In PAGE 8: ...Table2 : Parameters for performance model Algorithm A B blksize(bits) MD5 203656 86298 512 SHA1 77337 233082 512 RC5 init/encrypt 352114 40061 64 RC5 init/decrypt 352114 39981 64 IDEA encrypt 68289 79977 64 IDEA decrypt 385713 105430 64 RC4 69240 13743 8 Therefore, a more detailed model for the parameters a and b can be derived as follows: where aBASE and bBASE are the base parameters shown in Table 4, aMUL and bMUL are adjustments of those parameters, which take into account the presence of absence of a multiplication instruction, and aRISC and bRISC take into account the type of the microprocessor architecture (CISC/RISC). For algorithms not using multiplication (e.... ..."
Cited by 15

TABLE III Mapping of scheduling services to DiffServ Code Point Priority DSCP

in Low-cost QoS-enabled Wireless Network with Interworked WLAN and WiMAX
by Humaira Haffajee, H. Anthony Chan

Table 1: Comparison of the aproaches to sensor network reconfiguration System Platform System

in Conference Chairs
by V. Phoha, S. S. Iyengar, Les Guice, S. S. Iyengar, Vir V. Phoha, Guna Seetharaman, Kristen Martin, S. Vason, P. Varshney, N. Rao, R. Fehling, R. Brooks, T. Laurens, S. Park, R. Sastry, G. Allen, G. Seetharaman, T. Kosar, J. Monde, J. Tsai, K. Mori, P. Chen, D. Kim
"... In PAGE 9: ... PACKET FLOODING DISTRIBUTED DENIAL OF SERVICE ATTACKS In this attack, packets are sent to flood links and exhaust arc capacities. Table1 shows Blue configurations and tree diagram we use to illustrate a branch and bound solution as shown in Figure 2. Details on executing branch and bound search can be found in [7,8].... In PAGE 9: ... Details on executing branch and bound search can be found in [7,8]. Set of nodes BC1 BC2 BC3 BC4 A1 1-3,2-4 1-3 2-4,1-4 1-4 A2 2-4 2-4 1-3 A3 3-4 3-4,1- 4,4-5 Table1 Blue configurations and min-cut edges. Figure 2.... In PAGE 24: ... The additional protocol packets generated to re-organize the clusters in the event of node failure is maximum for grid deployment and insignificant in all other deployment strategies. Table1 shows that by adopting the maximum coverage approach (each cluster head forms a cluster by choosing geographically farthest nodes from its one hop neighbors) in the clustering algorithm we can form as many as twice the number of clusters with closest approach (each cluster head forms a cluster by choosing geographically closest nodes from its one hop neighbors) even when N=2. This justifies the large protocol overhead observed in case of maximum coverage approach.... In PAGE 62: ...Table1 . Comparison of Stream Hierarchy to Conventional Abstractions/Hierarchies Levels Lowest Level Highest Level Abstraction Inter-level Data Migration Memory Hierarchy n External Storage Subset/Cache/Buffer Fetch/Prefetch DBMS Data Hierarchy 3 Physical Storage External View Fetch, Prefetch Data Warehouse n Operational Data Cube/Multidimensional View Aggregation Stream Hierarchy 4 Sensor Data Visualization/Triggers Automatic Push There have been several DSMS projects: STREAM (developed at Stanford) supports SQL-like queries.... ..."

Table 1 - Hardware and Software Platforms.

in unknown title
by unknown authors
"... In PAGE 4: ... The VIOLA clients are equipped with a ReelMagic MPEG player. Table1 summarizes the hardware and software configurations of... ..."

Table 10: The execution time ratio after the two delay optimizations and loop merging the cost of the control structures cannot be neglected when small collections are used. A solution to this problem could be the development of a new control scheme based upon an automaton where each state would represent a di erent clock state con guration (in the way of temporal synchronous languages such as Lustre [2] and Signal [3]). But, because of 81/2 apos;s ability to mix di erent clocks, we should expect rather large automata. The current execution scheme corresponds to a sequential control ow. A promising approach for a better exploitation of the new parallel architectures would be to exploit a parallel control ow. The 81/2 team has already worked in this way, particularly in the mapping and scheduling problems [53] that will be integrated in the present compiler.

in Semantics and compilation of sequential streams into a static SIMD code for the declarative data-parallel language
by Dominique De Vito

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier Jonathan, Jonathan Babb, Matthew Dahl, Silvina Hanono, Anant Agarwal 1994
"... In PAGE 6: ... Sparcle is an 18K Sparc microprocessor with modifications to enhance its usefulness in a multipro- cessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation of these two designs.... ..."
Cited by 27

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier, Jonathan Babb, Matthew Dahl, Silvina Hanono, Anant Agarwal 1994
"... In PAGE 6: ... Sparcle is an 18K Sparc microprocessor with modifications to enhance its usefulness in a multipro- cessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation of these two designs.... ..."
Cited by 27

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier Jonathan, Jonathan Babb, Matthew Dahl, Silvina Hanono, David Hoki 1994
"... In PAGE 2: ... Sparcle [2] is an 18K Sparc microprocessor with modifications to enhance its use- fulness in a multiprocessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation Statistic Sparcle FPGAs 24 Avg.... ..."
Cited by 27

Table 1: Hardware Statistics for Simulation Acceleration

in The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment
by Russell Tessier , Jonathan Babb, Matthew Dahl, Silvina Hanono, Anant Agarwal
"... In PAGE 6: ... Sparcle is an 18K Sparc microprocessor with modifications to enhance its usefulness in a multipro- cessor environment. Table1 presents some basic statistics for these two designs when mapped to the emulation system for simulation acceleration. We have successfully used the system to accelerate circuit simulation of these two designs.... ..."
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