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Table 1: FinFET Device Parameters

in Design Trade-offs of a 6T FinFET SRAM Cell in the Presence of Variations
by Eric Chin, Mohan Dunga, Borivoje Nikolic

Table 1: Model finFET dimensions and thermal conductivities

in THERMAL AND SENSITIVITY ANALYSIS OF MULTI-FIN DEVICES
by unknown authors
"... In PAGE 2: ... SINGLE-FIN DISTRIBUTED THERMAL MODEL We intend to use the UTB device model to investigate the effects of fin layout, finFET sensitivity and device geometries on the max- imum temperatures of multi-fin devices. Using the device geome- tries in Table1 , we compared the temperatures obtained using the UTB model with ones obtained using ANSYS, a finite-element solver. The heat distribution obtained using ANSYS is shown in Figure 6.... In PAGE 4: ... Finally, we vary fin geometries and investigate the impact of gate length, gate height, fin width, fin height, and fin spacing on the temperature of multi-fin devices. Our baseline (nominal) device is a single fin (distributed channel model, rectangular fin extension) with the parameters shown in Table1 . Our data, when normalized, is in reference to this single-fin case.... ..."

Table 1 Device parameters of the Taurus FinFET model Device Parameters Values

in Width quantization aware FinFET circuit design,” Custom Integrated Circuit Conference
by Jie Gu, John Keane, Sachin Sapatnekar, Chris Kim 2006
"... In PAGE 1: ... The FinFET model has a symmetrical front and back metal gate which are tied together. Table1 lists the device parameters of the designed FinFET model used throughout this paper. III.... ..."
Cited by 1

Table 2. Testability of circuits optimized BDD circuit

in Experimental studies on test pattern generation for BDD circuits
by Junhao Shi, Görschwin Fey, Rolf Drechsler 2004
"... In PAGE 3: ... Note, that the mapping of BDDs onto the STD library can be seen as a worst case for BDD circuits as the realization of a MUX cell in multiplexor based design styles is much cheaper. In Table2 data regarding the testability is shown. The number of test patterns, caught faults and redundancies are given in column pattern, caught, red.... In PAGE 3: ... The list of test patterns calculated during test pattern generation was compacted using fault simulation on the reversed list afterward. Table2 shows that the optimized circuits can contain a large number of redundancies. The synthesis approach fa- cilitated by SIS does not take this aspect into account.... ..."
Cited by 1

Table 1. Synthesis results, B = m = n = 16 (optimized for area).

in Design Tradeoffs Using Truncated Multipliers in Fir Filter Implementations
by George Walters, E. George, Walters Iii, Michael Schulte
"... In PAGE 11: ... 4. RESULTS Table1 presents some representative synthesis results that were obtained from the synthesis tool, Leonardo, and the LCA300K 0.6 micron CMOS standard cell library.... ..."

Table 2: Technology Mapping results

in A Rapid Boolean Technology Mapping applicable to Power Minimization
by Ricardo Ferreira, A-m. Trullemans, Ricardo Jacobi
"... In PAGE 8: ... The results show that the Boolean approach reduces the number of matching algorithm calls, nd smaller area circuits in better CPU time, and reduces the initial network graph because generic 2-input base function are used. Table2 presents a comparison between SIS and Land for the library 44-2.genlib, which is distributed with the SIS package.... ..."

Table 1. Multiplier synthesis results Operand

in
by Robert D. Kenney, Michael J. Schulte
"... In PAGE 4: ...l1 micron CMOS standard cell library. Table1 shows the results of synthesis runs when the designs are optimized for delay. The delays for each operand size are very close, since the delay of the design is not very dependent on the width of the operands.... ..."

Table 1. Summary of comparison on MCNC benchmarks. Logic synthesis flow Stand. cells FPGAs

in DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
by Alan Mishchenko 2006
"... In PAGE 3: ... 4.2 Comparison using MCNC benchmarks In Table1 , we compare the average ratios of improvements achieved by technology mapping for standard cells and FPGAs after running several optimization scripts. The complete set of MCNC benchmarks [19] is used in this experiment.... In PAGE 3: ... The complete set of MCNC benchmarks [19] is used in this experiment. The results of mapping unoptimized circuits are used as the base for comparison (Line 1 of Table1 ). The optimization in SIS (script.... ..."
Cited by 28

Table 1. Summary of comparison on MCNC benchmarks. Logic synthesis flow Stand. cells FPGAs

in DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
by Alan Mishchenko 2006
"... In PAGE 3: ... 4.2 Comparison using MCNC benchmarks In Table1 , we compare the average ratios of improvements achieved by technology mapping for standard cells and FPGAs after running several optimization scripts. The complete set of MCNC benchmarks [19] is used in this experiment.... In PAGE 3: ... The complete set of MCNC benchmarks [19] is used in this experiment. The results of mapping unoptimized circuits are used as the base for comparison (Line 1 of Table1 ). The optimization in SIS (script.... ..."
Cited by 28

Table 1. Effective yield ratio with respect to standard synthesis optimization on IWLS93 circuits.

in Synthesis for Manufacturability: a Sanity Check
by Alessandra Nardi , Alberto L. Sangiovanni-Vincentelli 2004
"... In PAGE 5: ... heuristics (Figure 2.c and Table1 ). The last four colums of the chart correspond to different values of p using the heuristic in Equation (12).... In PAGE 5: ...euristics (Figure 2.c and Table 1). The last four colums of the chart correspond to different values of p using the heuristic in Equation (12). Table1 confirms the results pre- dicted in the previous Section: assuming yield follows a Poisson model, p = N leads to best results for effective yield. As an additional remark, the error due to the approx- imation described in Equation (12) is less than 0:1% with p = N, while it can reach values up to 20% by using p = 100N.... ..."
Cited by 2
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