Results 1 - 10 of 13,969

Expression and Loop Libraries for HighPerformance Code Synthesis

by Christopher Mueller, Andrew Lumsdaine - In: Proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing , 2006
"... Abstract. To simultaneously provide rapid application development and high performance, developers of scientific and multimedia applications often mix languages, using scripting languages to glue together high-performance components written in compiled languages. While this can be a useful developme ..."
Abstract - Cited by 3 (2 self) - Add to MetaCart
is an effective platform for optimizing serial and parallel applications without relying on intermediate languages. In this paper, we use the SPE to develop two code generation libraries, one for scalar and vector (SIMD) expression evaluation and another for parallel and high-performance loop generation. Using

Comparison of high-performance codes on AWGN channel with erasures

by Thorsten Hehn, Johannes B. Huber - In Proceedings of 4th International Symposium on Turbo Codes in connection with the 6th International ITG-Conference on Source and Channel Coding , 2006
"... This paper provides an overview of near Shannon-limit operating codes when transmitted over the additive white Gaussian noise (AWGN) channel with erasures. We compare the performance of standardized low-density parity-check (LDPC) codes and parallel-concatenated (turbo) codes to two progressive edge ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
This paper provides an overview of near Shannon-limit operating codes when transmitted over the additive white Gaussian noise (AWGN) channel with erasures. We compare the performance of standardized low-density parity-check (LDPC) codes and parallel-concatenated (turbo) codes to two progressive

Evaluation of a High Performance Code Compression Method

by Charles Lefurgy, Eva Piccininni, Trevor Mudge , 1999
"... Compressing the instructions of an embedded program is important for cost-sensitive lowpower control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the ins ..."
Abstract - Cited by 24 (0 self) - Add to MetaCart
the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal

Evaluation of a High Performance Code Compression Method

by unknown authors
"... Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the in ..."
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the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM’s PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal

Evaluation of a High Performance Code Compression Method

by unknown authors
"... Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the in ..."
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the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM’s PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal

Evaluation of a High Performance Code Compression Method

by unknown authors
"... Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the in ..."
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the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM’s PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal

A High-Level Approach to Synthesis of High-Performance Codes for Quantum Chemistry

by Gerald Baumgartner, David E. Bernholdt, Daniel Cociorva, Robert Harrison, So Hirata Chi-Chung Lam, So Hirata, Chi-chung Lam, P. Sadayappan, Marcel Nooijen, Russell Pitzer J. Ramanujam, J. Ramanujam - In Proc. of Supercomputing 2002 , 2002
"... This paper discusses an approach to the synthesis of high-performance parallel programs for a class of computations encountered in quantum chemistry and physics. These computations are expressible as a set of tensor contractions and arise in electronic structure modeling. An overview is provided of ..."
Abstract - Cited by 37 (15 self) - Add to MetaCart
of the synthesis system, that transforms a high-level specification of the computation into high-performance parallel code, tailored to the characteristics of the target architecture. An example from computational chemistry is used to illustrate how different code structures are generated under different

High-performance code generation for stencil computations on GPU architectures

by Justin Holewinski, Louis-noël Pouchet - In ICS , 2012
"... Stencil computations arise in many scientific computing do-mains, and often represent time-critical portions of applica-tions. There is significant interest in offloading these com-putations to high-performance devices such as GPU acceler-ators, but these architectures offer challenges for developer ..."
Abstract - Cited by 25 (2 self) - Add to MetaCart
Stencil computations arise in many scientific computing do-mains, and often represent time-critical portions of applica-tions. There is significant interest in offloading these com-putations to high-performance devices such as GPU acceler-ators, but these architectures offer challenges

Automatic Synthesis of High-Performance Codes for Quantum Chemistry Applications

by Gerald Baumgartner, David E. Bernholdt, Daniel Cociorva, Chi-chung Lam, J. Ramanujam
"... This paper discusses a program synthesis system to facilitate the generation of high-performance parallel programs for a class of computations encountered in quantum chemistry and physics. These computations are expressible as a set of tensor contractions and arise in electronic structure modeling. ..."
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. An overview is provided of the synthesis system under development, that will take as input a high-level specification of the computation and generate high-performance parallel code for a number of target architectures. Several components of the synthesis system are described, focusing on compile

Automatically Generated High-Performance Code for Discrete Wavelet Transforms

by Aca Gačić , Markus Püschel, José M. F. Moura
"... A growing number of performance-critical DSP application use the discrete wavelet transform (DWT), thus prompting the need for highly efficient DWT software implementations. Unfortunately, the rapid evolution of computing platforms and compiler technology makes carefully hand-tuned code obsolete alm ..."
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A growing number of performance-critical DSP application use the discrete wavelet transform (DWT), thus prompting the need for highly efficient DWT software implementations. Unfortunately, the rapid evolution of computing platforms and compiler technology makes carefully hand-tuned code obsolete
Results 1 - 10 of 13,969