"... In PAGE 79: ...Peak-to-peak jitter is measured for a clock receiver with a 7.4-GHz input at the transmitting antenna, and is shown in Table5 -1 as a percentage of the 925-MHz local clock. The corresponding signal-to-noise ratio at the input of the frequency divider is cal- culated using (5.... In PAGE 79: ... The corresponding signal-to-noise ratio at the input of the frequency divider is cal- culated using (5.1) and is also listed in Table5 -1. The noise generators are first driven by the on-chip ~1-GHz VCO operating at its maximum frequency, and a 15-dBm signal is GSSG Probe SpectrumAnalyzer HP 8653E OscilloscopeHP 54120B HP 54121A Clock Receiver Balun and SS Probe Splitter Power Amplifier Signal Generator On-chip Figure 5-7... ..."

"... In PAGE 7: ... The column Num. in Table2 shows the number of changeable connections in a network, and the column Ratio in Table 2 shows the ratio(%) of changeable connections to all connections in the network. The mean value of the ratios was 73.... In PAGE 7: ...8%. The column CPU in Table2 shows the CPU run-time (sec.) on a SPARC station 20 to check all connections in the network.... ..."

"... In PAGE 16: ... SCLK divider values are 1 through 15. Table6 illustrates typical system clock ratios: Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV).... ..."

"... In PAGE 18: ...meet the specified noise magnitude. Table8 summarizes the decoupling assignment and power-supply components in this system so that direct comparisons to a similar table in [1] can be made. Timing analysis The cycle time of the synchronous interconnects between chips is determined by the time-of-flight on the package interconnect, the on-chip delay including the driver and receiver, the timing differences in the clock tree (clock skew), the long-term PLL jitter for the driver/receiver chips, the impact of coupling and power noise on the signal arrival times, and a safety margin for the engineering testing [1].... ..."

"... In PAGE 11: ... To prevent packet loss, we assume buffer space is allocated on a per connection basis at each server during connection establishment time. Table2 presents the end-to-end characteristics and buffer space requirement of a connection when different work- conserving service disciplines are used. The table can be interpreted as the following.... In PAGE 17: ... It can be shown that the following holds According to Table 4, an end-to-end delay bound of can be provided to the connection + ET=, P3 in both cases. Compared to Table2 , the above delay bound is identical to that provided by WFQ, WF2Q, and virtual clock servers. The about assignments are just examples to illustrate the flexibility of rate-controlled service disciplines.... ..."

"... In PAGE 20: ... Table 8 lists the simulated jitter figures (including a fixed 15 ps PLL setup jitter) and the resulting skew budgets including jitter and other sources of clock and data delay variation. TABLE8 . Skew Budgets with Data Delay Variations and Simulated Jitter (ps) Gater SLCB Repeater PD 64 76 117 120 151 188 232 244 tjitter setup tskew setup Statistical Clock Skew Modeling with Data Delay VariationsMarch 21, 2001... ..."

"... In PAGE 6: ... We sus- pect that the requirement of word order may affect the grammatically. Table 1 and Table3 also indi- cates that our new method achieved the importance of words are outperform than the baseline algorithm due to semantic information. This was because our method using semantic information to avoid deleting important words.... In PAGE 6: ... The comparison row in the Table 1 and the Table 2 also reported that the baseline yields a shorter output than syntax control method. Table3 shows that when we selected randomly 32 sentence pairs from 100 pairs of sentences those had words order between input and output are different, we have the syntax method change a bit while the baseline method achieved a low result. This is due to the syntax control method using rule knowledge based while the baseline was not able to learn with that corpus that.... ..."

"... In PAGE 20: ... Table8 lists the simulated jitter figures (including a fixed 15 ps PLL setup jitter) and the resulting skew budgets including jitter and other sources of clock and data delay variation. TABLE8 . Skew Budgets with Data Delay Variations and Simulated Jitter (ps) Gater SLCB Repeater PD 64 76 117 120 151 188 232 244 tjitter setup tskew... ..."

"... In PAGE 5: ...scilloscope. For observation and control the signal was also displayed on a monitor. With the original signal on one input channel and the delayed signal on the other channel the oscilloscope showed the time spent on the encoding and decoding process. The jitter was derived using 100 samples of measured delay values and was calculated as the difference between maximum and minimum delay within the obtained value range ( Table1 ). The indicated values include both encoding and decoding times.... ..."

"... In PAGE 9: ...Table 1: Special Cases of the Delay-Jitter Controlling Regulator The definition of the delay-jitter controlling policy is general. As shown in Table1 , regulators used in previously proposed non-work-conserving such as RCSP [28], Jitter-EDD [26], and Stop-and-Go [8] are its special cases. In RCSP, i;j in (3) is 0.... In PAGE 9: ...pecial cases. In RCSP, i;j in (3) is 0. In Jitter-EDD, ETk i;j is defined to be ATk i;j + Aheadk i?1;j, where ATk i;j is the arrival time of the kth packet at the ith server, and Aheadk i?1;j is the amount of time the kth packet was ahead of schedule at the i ? 1th server. It is easy to show that this definition is equivalent to the definition in Table1 when the link delay is constant, or i = i;j. In Stop-and-Go, the frame time Tm is the local delay bound for the connection at all servers along the path.... ..."