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Results 11 - 20
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1,127
Analog Simulator Tests Qualify Distance Relay Designs to Today’s Stringent Protection Requirements
"... Abstract—Deregulation, increased loads, and limited resources/rights-of-way available for the building of new transmission lines are routinely pushing modern power transmission networks to operating limits. New generations of microprocessor relays provide design opportunities that help stressed tran ..."
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Abstract—Deregulation, increased loads, and limited resources/rights-of-way available for the building of new transmission lines are routinely pushing modern power transmission networks to operating limits. New generations of microprocessor relays provide design opportunities that help stressed
Quality-of-service driven power and rate adaptation over wireless links
- IEEE TRANS. WIRELESS COMMUN
, 2007
"... We propose a quality-of-service (QoS) driven power and rate adaptation scheme over wireless links in mobile wireless networks. Specifically, our proposed scheme aims at maximizing the system throughput subject to a given delay QoS constraint. First, we derive an optimal adaptation policy by integrat ..."
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Cited by 74 (14 self)
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significant impact on QoS-driven power and rate adaptations. The higher the correlation is, the faster the power-control policy converges to the total channel inversion when the QoS constraint becomes more stringent. Finally, we conduct simulations to verify that the adaptation policy proposed for Markov
Planning UMTS Base Station Location: Optimization Models with Power Control and Algorithms
- IEEE Transactions on Wireless Communications
, 2003
"... Classical coverage models, adopted for second-generation cellular systems, are not suited for planning universal mobile telecommunication system (UMTS) base station (BS) location because they are only based on signal predictions and do not consider the traffic distribution, the signal quality requir ..."
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Cited by 66 (12 self)
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requirements, and the power control (PC) mechanism. In this paper, we propose discrete optimization models and algorithms aimed at supporting the decisions in the process of planning where to locate new BSs. These models consider the signal-to-interference ratio as quality measure and capture at different
Synthesis Of Embedded Software From Synchronous Dataflow Specifications
- JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS
, 1999
"... The implementation of software for embedded digital signal processing (DSP) applications is an extremely complex process. The complexity arises from escalating functionality in the applications; intense time-to-market pressures; and stringent cost, power and speed constraints. To help cope with such ..."
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Cited by 95 (17 self)
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The implementation of software for embedded digital signal processing (DSP) applications is an extremely complex process. The complexity arises from escalating functionality in the applications; intense time-to-market pressures; and stringent cost, power and speed constraints. To help cope
Towards a unified radio power management architecture for wireless sensor networks
- in WWSNA
, 2007
"... Abstract: In many wireless sensor networks, energy is an extremely limited resource. While many different power management strategies have been proposed to help reduce the amount of energy wasted, application developers still face two fundamental challenges when developing systems with stringent pow ..."
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Cited by 12 (5 self)
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Abstract: In many wireless sensor networks, energy is an extremely limited resource. While many different power management strategies have been proposed to help reduce the amount of energy wasted, application developers still face two fundamental challenges when developing systems with stringent
Chrysso: An Integrated Power Manager for Constrained Many-Core Processors
"... Modern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore’s Law). Existing many-core power management tech-niques such as chip-wide/per-core DVFS, and core and cache adapta ..."
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adaptation are quite e↵ective in isolation at moderate to high power budgets. However, for future many-core chip, the ex-isting techniques do not scale well to large core counts, small time slices and stringent power budgets. We need a new solu-tion that combines di↵erent adaptation and reconfiguration
Test Cost Efficiency Exploration for CMT Processors
"... Abstract --Chip Multi-Threading (CMT) is an architecture that can achieve overall high performance by exploiting high bandwidth rather than high frequency, thus reduce hardware complexity and power. Test cost of this architecture also can be reduced by efficiently utilizing its communication channe ..."
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channel bandwidth during test. Because CMT architectures are designed low-power in nature, its testing should also be conducted under stringent power constraints. This paper discusses these above problems and proposes a cost-efficient test scheme. Experimental results show that our test scheme can achieve
Design and Analysis of CMOS Full Adders for Low Power and Low Frequency of Operation for Scavenged-Power Wireless Sensor Networks
, 2007
"... While many VLSI applications require or benefit greatly from low power consumptions, scavenged power wireless sensor networks have far more stringent power requirements, often in the sub-uW range. At these power levels, static and leakage power consumption can form significant amounts of the total p ..."
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While many VLSI applications require or benefit greatly from low power consumptions, scavenged power wireless sensor networks have far more stringent power requirements, often in the sub-uW range. At these power levels, static and leakage power consumption can form significant amounts of the total
Wireless sensor networks: applications and challenges of ubiquitous sensing
- IEEE Circuits and Systems Magazine
, 2005
"... Sensor networks offer a powerful combination of distributed sensing, computing and communication. They lend themselves to countless applications and, at the same time, offer numerous challenges due to their peculiarities, primarily the stringent energy constraints to which sensing nodes are typicall ..."
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Cited by 79 (0 self)
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Sensor networks offer a powerful combination of distributed sensing, computing and communication. They lend themselves to countless applications and, at the same time, offer numerous challenges due to their peculiarities, primarily the stringent energy constraints to which sensing nodes
The chip-scale atomic clock –low-power physics package
- Proc. of the 36th Annual Precise Time and Time Interval (PTTI) Meeting
, 2004
"... We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, 2/110y 106)( −−×< ττσ, with a total power consumption of less than 30 mW and overall device volume < 1 cm3. The stringent power requirement dominates th ..."
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Cited by 5 (0 self)
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We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, 2/110y 106)( −−×< ττσ, with a total power consumption of less than 30 mW and overall device volume < 1 cm3. The stringent power requirement dominates
Results 11 - 20
of
1,127
