"... In PAGE 6: ... Once again, we attain almost the same diagnostic resolution after the compactiona0 the values of Rfp before and after compaction are almost the same in Table 2. In Table3 , we present results on the total dictionary size and the DE values when we take into account the dictionaries for all the three stages. We also compare our results to a recent compact dictionary approach based on output compaction [8].... In PAGE 6: ...a1 It can be seen that even though our method uses a larger amount of BIST vectors than the ATPG vectors in [8], the overall dictionary size is smaller, and diagnostic resolution is in most case comparable to that in [8]. Finally, in order to demonstrate the effectiveness of using LFSR-compaction for a dictionary based on ATPG vectors, we apply the compaction procedure on the dictionaries referred to in Columns 5 and 6 of Table3 . We show the Circuits Pass/fail diction- ary size before compac- tion (Mbits) Overall size after compac- tion (Mbits) DE after compac- tion Size of diction- ary in [8] (Mbits) DE for diction- ary in [8] Diction- ary size in [8] after LFSR- based compac- tion (Mbits) DE in [8] after compac- tion s9234 58.... ..."

"... In PAGE 5: ... A 12-bit version of each generator was used; for the LFSR-based gen- erators it is easy to extend the test length by using a larger LFSR. Table4 shows the number of faults that remained undetected after 4k vectors; in Table 5 these numbers are normalized by the number of adders and subtractors used in the design. In the highpass and bandpass designs, the LFSR-1 and LFSR-D generators give very similar performance.... ..."

"... In PAGE 5: ... A 12-bit version of each generator was used; for the LFSR-based gen- erators it is easy to extend the test length by using a larger LFSR. Table4 shows the number of faults that remained undetected after 4k vectors; in Table 5 these numbers are normalized by the number of adders and subtractors used in the design. In the highpass and bandpass designs, the LFSR-1 and LFSR-D generators give very similar performance.... ..."

"... In PAGE 5: ... A 12-bit version of each generator was used; for the LFSR-based gen- erators it is easy to extend the test length by using a larger LFSR. Table4 shows the number of faults that remained undetected after 4k vectors; in Table 5 these numbers are normalized by the number of adders and subtractors used in the design. In the highpass and bandpass designs, the LFSR-1 and LFSR-D generators give very similar performance.... ..."

"... In PAGE 5: ... A 12-bit version of each generator was used; for the LFSR-based gen- erators it is easy to extend the test length by using a larger LFSR. Table4 shows the number of faults that remained undetected after 4k vectors; in Table 5 these numbers are normalized by the number of adders and subtractors used in the design. In the highpass and bandpass designs, the LFSR-1 and LFSR-D generators give very similar performance.... ..."

"... In PAGE 8: ...075 Table 4: The technology library used in measurements. Table5 gives the number of test vectors and the fault cover- age obtained from different schemes for single faults. This ta- ble compares our test scheme with LFSR based pseudo-random test generation and with algorithmic test generation.... ..."

"... In PAGE 5: ... The fault coverage of such random functional test patterns has been compared to the fault coverage achieved by running one of the most efficient commercial gate-level TPG, which performs at first random generation followed by deterministic test generation. Results of this comparison are reported in Table3 , where all versions of each bench- mark are identified by a suffix composed of the data size and the number of control steps: e.g.... In PAGE 5: ...nd the number of control steps: e.g., the first benchmark of Table 1 is referred to as diffeq 8 4. Table3 shows the number of stuck-at faults (Tot.F.... ..."

"... In PAGE 8: ... Deterministic test 4. I10 test Table4 shows TPG statistics for the MBA chip. Outlook We have described a standard-cell-based VLSI design system producing results which are competitive with custom design solutions in terms of density, in a very short turnaround time.... ..."

"... In PAGE 7: ... All experiments are performed on an IndyPC- R4600 workstation from Silicon Graphics. Table 3: Characteristics of industrial circuits Circuit 3-state elements p1411 2 3-state busses at PIs p1641 1 3-state bus at PIs p2725 7 trinvs, 20 tris, 8 3-state busses p8052 711 3-state switches, 397 3-state busses p31666 3 ODNs, 34 tris, 16 3-state busses p34595 2076 3-state switches, 675 3-state busses p36615 30 tris, 18 3-state busses p60667 289 3-state switches, 290 3-state busses p90685 454 3-state switches, 137 3-state busses p93140 454 3-state switches, 138 3-state busses Experiment 1 Table4 shows the experimental re- sults for compact TPG without redundancy identi - cation for some industrial circuits. The rst column gives the circuit name.... ..."

"... In PAGE 5: ... The processor assignment following our heuristic keeps the graph unchanged in this case. The priority calcu- lation is demonstrated in Table1 which shows the calculated values of the top Level and bottom Level of each task. The priority is determined as the sum of these two parameters.... ..."