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Table 2: Implementation Differences between the Software-only and Hardware-assisted Versions of Real-Time Mach

in Quantitative Analysis of Hardware Support for Real-Time Operating Systems
by Saurav Chatterjee, Jay Strosnider 1996
"... In PAGE 12: ... higher priority thread that becomes eligible for execution. A thread may also block voluntarily, e.g., waiting for a semaphore. Fixed-priority scheduling is implemented in the software-only version of Real-Time Mach using two software-maintained queues ( Table2 ). The run queue contains threads, in priority order, that are eligible for execution.... In PAGE 13: ... This implementation exclusively executes machine instructions found on any RISC microprocessor. The hardware-assisted version of Real-Time Mach substitutes 80960XA-specific hardware-assisted instructions for a series of generic RISC instructions, as shown in Table2 . Sections 4 and 5 will then quantitatively examine the impact of hardware support on operating system and application performance.... ..."
Cited by 2

Table shows the latency in cycles for different instructions and for register file spilling and reloads. Most of these numbers were taken from timing simulations [43] of a Sparc [79] processor, with Sparc2 cache sizes and hit rates. Three different sets of cycle counts are shown: timing for the NSF; for a segmented file with hardware assist for spills and reloads; and for a segmented file that spills and reloads using software trap routines.

in The Named-State Register File
by Peter Robert Nuth, Peter Robert Nuth, Peter Robert Nuth 1993
Cited by 5

Table shows the latency in cycles for different instructions and for register file spilling and reloads. Most of these numbers were taken from timing simulations [43] of a Sparc [79] processor, with Sparc2 cache sizes and hit rates. Three different sets of cycle counts are shown: timing for the NSF; for a segmented file with hardware assist for spills and reloads; and for a segmented file that spills and reloads using software trap routines.

in IBM Corporation, and AT&T. The Named-State
by The Named-state, Register File, Peter Robert Nuth, Peter Robert Nuth, Peter Robert Nuth

Table 6: Utilization for the Hardware-Assisted Version of Real-Time Mach

in Quantitative Analysis of Hardware Support for Real-Time Operating Systems
by Saurav Chatterjee, Jay Strosnider 1996
"... In PAGE 4: ... An event-driven timer implementation eliminates this error. As shown in Table6 , the predicted and measured breakdown utilization for the avionics task set were approximately equal. The predicted utilization was more pessimistic, as expected, by approximately 1%.... ..."
Cited by 2

Table 8: Rendering times in seconds using the different hardware-assisted splat- ting strategies and 3D texture mapping.

in Hardware and software improvements of volume splatting
by E. Vergés, S. Grau, D. Tost 2006
"... In PAGE 10: ... CES costs are lower than those of OSS and ISS because there is no plane composition in that method. Table8 shows the run-time of the hardware accelerated versions of these algorithms using point-sprite, multi-texturing and FBOs. The hardware optimizations reduce between one half and two thirds the computational cost for the small and regular sized models.... ..."

Table 3: Timing results of incremental pre-integration of the transfer function on the GPU (in milliseconds).

in unknown title
by unknown authors 2005
"... In PAGE 7: ... Modifying the opacity or loading a new colormap triggers a transfer function update on the GPU. The per- formance of hardware-assisted incremental pre-integration is given in Table3 . The results represent the time required to regenerate an 8-bit RGBA texture.... ..."
Cited by 26

Table 2. Comparative timings, in seconds, for visibility ordering using five methods: (1) the sort reported in Stein et al. [20], (2) the multi-tiled sort of Williams et al. [26], (3) the XMPVO algorithm of Silva et al. [18], (4) the BSP-XMPVO algorithm of Comba et al. [6]. (5) and (6) are our results under two different window resolutions. We separate the time sorting the boundary cells took from the time it takes to the MPVO relations, as to highlight the different overheads. The first three timings were performed on an R10000 CPU of an SGI Power Onyx; BSP-XMPVO was timed on a 333MHz PowerPC 604. (5) and (6) were timed on an R12K CPU of an SGI Octane with MXE graphics.

in A Hardware-Assisted Visibility-Ordering Algorithm with Applications to Volume Rendering
by Shankar Krishnan, Cláudio T. Silva, Bin Wei 2001
"... In PAGE 8: ... It is quite simple to replace the XMPVO sorting with our new approach. We present the performance of our hardware-assisted visibility ordering algorithm com- pares to these techniques in Table2 . We also include two previous techniques for exact polyhedral cell sorting, the algorithm of Stein et al.... ..."
Cited by 14

Table 2. Comparative timings, in seconds, for visibility ordering using five methods: (1) the sort reported in Stein et al. [20], (2) the multi-tiled sort of Williams et al. [26], (3) the XMPVO algorithm of Silva et al. [18], (4) the BSP-XMPVO algorithm of Comba et al. [6]. (5) and (6) are our results under two different window resolutions. We separate the time sorting the boundary cells took from the time it takes to the MPVO relations, as to highlight the different overheads. The first three timings were performed on an R10000 CPU of an SGI Power Onyx; BSP-XMPVO was timed on a 333MHz PowerPC 604. (5) and (6) were timed on an R12K CPU of an SGI Octane with MXE graphics.

in A Hardware-Assisted Visibility-Ordering Algorithm with Applications to Volume Rendering
by Shankar Krishnan, Claudio T. Silva, Bin Wei 2001
"... In PAGE 8: ... It is quite simple to replace the XMPVO sorting with our new approach. We present the performance of our hardware-assisted visibility ordering algorithm com- pares to these techniques in Table2 . We also include two previous techniques for exact polyhedral cell sorting, the algorithm of Stein et al.... ..."
Cited by 14

Table 2: Summary of available DMA registration strategies

in A New DMA Registration Strategy for Pinning-Based High Performance Networks
by Christian Bell, Dan Bonachea
"... In PAGE 5: ....3. Firehose and Existing Pinning-based DMA strategies Although hardware-assisted memory registration eases the port- ing task for GAS languages, most existing high performance NICs are not equipped with the sophisticated memory interface hardware required to make this approach work. Table2 provides a sum- mary of current DMA registration strategies, separating hardware- assisted from software-based approaches. Their advantages and disadvantages are explained below.... ..."

Table 32. Ecosystem Services enhanced by Habitat Protection and Conservation Measures in the Nearshore

in Funded by: WRIA 9 Watershed Forum of Local Governments through the King Conservation District Prepared by: Asia Pacific Environmental Exchange
by Sound Watershed, David Batker, Elizabeth Barclay, Roelof Boumans, Terri Hathaway, Assistance From Erin Burgess, Dawn Shaw, Shuang Liu 2005
"... In PAGE 4: ... Ecosystem Goods and Services provided by Landscape Features Table 31. Ecosystem Goods and Services Provided by Habitat Types Table32 . Ecosystem Services enhanced by Habitat Protection and Conservation Measures in the Nearshore Table 33.... In PAGE 71: ... Table32 shows the ecosystem services enhanced by the restoration of sediment processes and creation of floodplains, marshes, flats, deltas, spits and side channels. The double star indicates a great increase in value.... ..."
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