"... In PAGE 4: ... The faults were injected at the beginning of the first execution of each routine. The fault injection simulations were allowed to continue until one of three things happened: 1) the ERRORS routine (see Table1 ) was called, 2) the fault was detected by the watchdog timer, or 3) the end of the routine was reached. If either of the first two events occurred, then the fault was said to be detected.... ..."

"... In PAGE 9: ... Some requests in GREEDY-ORDER and GREEDY-ORDER-IDEAL take thousands of cycles and even exceed the per-request watchdog timer of 80,000 cycles we use in the simulator. Table5 shows the average number of retries used for each coherence request and the maximum observed. Misses to the MIC account for most of the actual number of retries (not shown) even though the hit rate of each 128KB MIC is 89-91% for all workloads.... ..."

"... In PAGE 9: ... Conversely, when the FPGA-based approach is exploited, the average time for one run of the program reduces to about 30ms, with a speed-up factor of about 4,000. The results coming from the fault injection experiments are summarized in Table2 , where the effects of 100,000 random faults are reported. Faults classified as Detected have triggered the Error Detection Mechanism the system embeds, which consists in a watch-dog timer.... ..."

"... In PAGE 31: ... These registers include status, interrupt and timer control, stack pointer, GPIO (General- Pourpose Input and Output) and SPI (Serial Programming Interface) and UART registers. Table2 presents the I/O registers for the AT90S8515 MCU. Unused and reserved locations... ..."

"... In PAGE 8: ... The purpose was twofold: rst, test whether, de- spite the overhead, the approach is practical, and second, whether the number of false alarms is low enough for the approach to be useful. The results of the experiments are summarised in Table1 . All experiments were run using Ciao Prolog 1.... ..."

"... In PAGE 25: ... The circuit diagram in Figure 23 shows the reset logic. Table5 defines the timing and electrical parameters of the reset circuitry. 25... In PAGE 27: ... As shown in Figure 23, an internal timer clocked from the Watchdog Timer Oscillator pre- vents the MCU from starting until after a certain period after VCC has reached the Power- on Threshold voltage (VPOT), regardless of the VCC rise time (see Figure 24). The Fuse bits SUT1 and SUT0 are used to select start-up time as indicated in Table5 . A 0 in the table indicates that the fuse is programmed.... In PAGE 37: ... The wake-up period is defined by the same SUT fuses that define the Reset Time-out period. The wake-up period is equal to the clock reset period, as shown in Table5 on page 27. If the wake-up condition disappears before the MCU wakes up and starts to execute, e.... In PAGE 104: ...UT1..0 Fuses: Determine the MCU start-up time. See Table5 on page 27 for further details. Default value is unprogrammed ( 11 ), which gives a nominal start-up time of 16 ms.... ..."

"... In PAGE 13: ... Therefore, bit TR2 must be set, separately, to turn the timer on. See Table5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a... ..."

"... In PAGE 13: ... There- fore, nodes that have negative ratings should have their ratings slowlyincreased or set back to a non- negative value after a long timeout. As shown in Table1 , the pause time of zero indicates that the nodes are in a constant motion and there is no pause time before and in between Table 1 Maximum and minimum network throughput with both watchdog and pathrater on... ..."