"... In PAGE 6: ...ompared to the clock periods proposed by V. Agarwal et. al. [16] for the corresponding technology and given in Table 7. Table8 shows wake-up penalties in terms of clock cycles. Our hspice simulations using the predictive technologies tool [1] reveal that the wake up penalty from T2 level is 1 cycle and is 2 cycles from both T3 and T4.... ..."

"... In PAGE 6: ... SIMULATION RESULTS We used HSPICE to find the wake up time and energy consumption during mode transition for a number of circuits from ISCAS benchmark suite for a 90nm CMOS technology. Table1 shows the experimental results in terms of the wake up time and energy consumption for a number of benchmarks when we use the conventional MTCMOS as well as the charge recycling MTCMOS. We observe from the table that energy saving during the mode transition is always more than 40% while the wake up time usually remains the same or improves slightly.... ..."

"... In PAGE 21: ... Maximum ground and supply currents (in mA). Table3 shows the wakeup time and the product of the maximum ground current and the wake up delay for all techniques. In terms of the product of maximum ground current and wake up time, again our proposed techniques (WS and/or ISTT) are superior to the previous ones by between one to two orders of ... ..."

"... In PAGE 23: ... Wake up time (pico Seconds), maximum ground current (mA) and their product (pico Coulombs). Comparing the products of maximum ground current and wake up time of our method in Table 3 and those in Table5 , we conclude that our techniques maintain the advantage (between one and two orders of magnitude) over Staircase-SS and Parallel-ST techniques even when they are implemented in a single cycle by between one and two orders of magnitude. Note that the wakeup times reported in Table 5 were calculated as the summation of the time required to apply the wakeup signals and the time required for all nodes in the circuit to settle.... In PAGE 23: ... Comparing the products of maximum ground current and wake up time of our method in Table 3 and those in Table 5, we conclude that our techniques maintain the advantage (between one and two orders of magnitude) over Staircase-SS and Parallel-ST techniques even when they are implemented in a single cycle by between one and two orders of magnitude. Note that the wakeup times reported in Table5 were calculated as the summation of the time required to apply the wakeup signals and the time required for all nodes in the circuit to settle. As stated earlier, it is not possible to eliminate the short circuit current inside cells with multiple logic stages.... ..."

"... In PAGE 6: ...ycles per ref. [5].) Next, we measured the maximum ground current and report the product of this current and the single-cycle wakeup time. The results are reported in Table4 . Comparing the products of maximum ground current and wake up time of our method in Table 3 and those in Table 4, we conclude that our techniques maintain the advantage (between one and two orders of magnitude) over Staircase-SS and Parallel-ST techniques even when they are implemented in a single cycle by between one and two orders of magnitude.... In PAGE 6: ... The results are reported in Table 4. Comparing the products of maximum ground current and wake up time of our method in Table 3 and those in Table4 , we conclude that our techniques maintain the advantage (between one and two orders of magnitude) over Staircase-SS and Parallel-ST techniques even when they are implemented in a single cycle by between one and two orders of magnitude. Note that the wakeup times reported in Table 4 were calculated as the summation of the time required to apply the wakeup signals and the time required for all nodes in the circuit to settle.... In PAGE 6: ...akeup time. The results are reported in Table 4. Comparing the products of maximum ground current and wake up time of our method in Table 3 and those in Table 4, we conclude that our techniques maintain the advantage (between one and two orders of magnitude) over Staircase-SS and Parallel-ST techniques even when they are implemented in a single cycle by between one and two orders of magnitude. Note that the wakeup times reported in Table4 were calculated as the summation of the time required to apply the wakeup signals and the time required for all nodes in the circuit to settle. 7.... ..."

"... In PAGE 22: ... We also used SCS algorithm for turning on the benchmark circuits. Table4 compares the wakeup times and maximum ground currents of SCS and WS algorithms. The table shows that the SCS algorithm improved the wakeup delay by 10%-15% over the WS algorithm while maintaining approximately the same IMAX.... ..."

"... In PAGE 12: ...hysical training, starts the second month. Each day begins at 5:00 a.m. and ends at 9:00 p.m. A breakdown of the weekday schedule appears in Table2 . The largest portion of each weekday is spent in school.... ..."