"... In PAGE 8: ...wo Iblocks ahead). As mentioned in Section 3.2, our prefetching is accurate in that every block prefetched is actually accessed and no unnecessary memory traffic is gen- erated. Cipher 3DES 7364 RC6 2804 IDEA 4768 RC4 2208 Mars 2614 Rijndael 1906 Blowfish 1998 Twofish 1926 TABLE2 . CPU Cycles to encrypt a cache line.... ..."

"... In PAGE 4: ... Active Input Specifications Table 5. Measurement Parameters Table6 . Serial Infrared Specifications Table 7.... In PAGE 33: ...ppendix B is Informative, not Normative {i.e., it does not contain requirements, but is for information only}. Specifications in Table6 are derived from tables earlier in the document. The link implementations in this appendix are examples only.... ..."

"... In PAGE 6: ... We found similar distributions in the rest of the samples. Table2 shows the reference counts of eight trans- action types in each of the 12 trace samples. We focus on the following classes of bus transactions: reads, writes (read-excl, write/inv), upgrades, and write/ flushes (essentially due to IO write).... In PAGE 36: ... To quantify this effect, we evaluated our workloads for different numbers of simulated transac- tions. Table2 shows some architectural characteristics, computed from an average of twenty OLTP simulations on a 16-processor system. We had initially hoped that the runtime statistics would converge as we ran longer simulation.... In PAGE 36: ...5% of release consistent systems. Keeton et al. [9] study the effects of out-of-order speculative execution on multiprocessor database workloads using hardware performance counters. Dedicated snooping hardware Table2 . Some OLTP properties for different simulation lengths Number of simulated transactions 200 400 600 800 1000 1200 System cycles per transaction 4.... In PAGE 42: ...6% of the total variance. After vari- max rotation, the first component is positively dominated, see Table2... In PAGE 43: ...2% of the total variance. After varimax rotation, the first component is positively dominated, see Table2 , by the amount of ILP, the percentage of arithmetic operations and the D-cache miss rate; and negatively dominated by the branch prediction accuracy of the gshare branch predictor and the percentage of logical operations. The second com- ponent is postively dominated by the I-cache miss rate and negatively dominated by the percentage of shift and byte manipulation operations.... In PAGE 43: ...2% of the total variance. Af- ter varimax rotation, the first component is positively domi- nated, see Table2 , by the branch prediction accuracy and the percentage of logical operations. The second princi- pal component is positively dominated by the I-cache miss rates.... In PAGE 45: ...95 0.07 Table2 . The factor loadings of the principal components after varimax rotation for li, gcc, postgres and all the benchmark-input tuples, from left to right respectively.... In PAGE 52: ... We compare ServBench programs to SPECint programs as well. Table2 shows the size of the C source code and compiled executable of each benchmark program in both ServBench and SPECint. The object code size does not include dynamically linked libraries.... In PAGE 52: ...ijpeg 31,200 594000 Tget 174 7960 129.compress 19,300 81700 Average 825 28679 Average 48700 678000 Table2 . Code sizes of ServBench and SPECint ServBench Instructions at Least once Instructions For 99% SPECint Instructions at Least once Instructions For 99% Fmt 18400 1112 126.... In PAGE 56: ...5 2 8k 16k 32k 64k 128k 256k IPC DCache ICache Figure 14. Different Impacts of L1 Caches on IPC Based on the above observations, when we combine the results of Table2 and Table 3 with those in Figure 2, we propose that these micro kernels be put in a part of the instruction cache which is not replaced to make room for other instructions. 5.... In PAGE 85: ... The processor and system parameters were chosen to reflect typical sys- tems in the near future. Table2 summarizes the base- line processor parameters used in our validation. We use a constant 400 cycle memory latency for the base- line configuration.... In PAGE 85: ...4% for dual thread Trace-B after we added store burstiness to the queueing model. Table2 :Processor Parameters Instruction Issue Buffer 128 entries L2 Load Buffer 32 entries Store Buffer 32 entries L2 cache 1MB, 4-way set associative L3 cache 32 MB, direct mapped Table 3: Comparison of IPC and number of outstanding Loads and Stores Single Thread Queueing/ Cycle Accurate Dual Thread Queueing/ Cycle Accurate IPC Trace-A Trace-B -0.43% 9.... In PAGE 97: ... Though they are not detailed enough, some understanding can be obtained. Table2 lists the break down of instruction types and corresponding miss rates. We will discuss the comparison between LVCSR and other SPEC benchmark programs later.... In PAGE 98: ...27% 35% 6.8% 38% 13% 96% 52% Table2... In PAGE 109: ... When the serialization is removed, then two or more processors use the cache lines at once, so they fre- quently steal the lines from each other before any of them can finish working with the line, increasing the amount of sharing. Table2 shows the number of serializations that occur in each workload. The processors do not need to add a memory barrier each time that they reach a serialization point.... In PAGE 116: ... 5.1 Characteristics Table2 sorts the queries in decreasing order based on the frac- tion of total query execution time spent in the pread system call obtained from earlier profile results. We can see that pread is a significant portion of the execution time in many queries.... In PAGE 117: ...1 3.5 Table2 : pread as a percentage of total execution time to lower or hide disk access costs, but to optimize the pread system call itself. In the interest of space, We focus on query Q6 which incurs the maximum pread overhead in the rest of this section.... ..."

"... In PAGE 14: ...ig. 10. The corresponding VLSI test chip for r =1,2,4or8. 4.2 Performance Evaluation The evaluation of hardware requirements and speed comparisons for a variety of parallel-input combinations for Type-I implementation based the CRC-32 generator polynomial [11] is shown in Table3 , in which the area of controlling switches is ignored in the comparison. The total gate counts (GC) are calculated based on the COMPASS cell library [14] in terms of the 2-input NAND gates and the hardware overhead (HO) is normalized with respect to the serial-input implementation.... ..."

"... In PAGE 11: ... 5 Experimental Results The experiments in Sections 5 and 6 were performed using five different graphs arising in finite element applications. They are enumerated and described in Table1 . METIS was originally used on the input graphs to obtain a 128-way partition.... ..."

"... In PAGE 2: ...3 Flexible pointer format To illustrate the advantage of having multiple formats for the serialized representation, assume we have a table potab having an XMLType column po which uses CLOB storage. Now consider the query in Table1 that extracts the purchase order number, the shipping address street, city and state, using XPath expressions embedded inside the Extract function. Extract operations can be complex navigational operations, and are often performed by manifesting the XML as a DOM tree for CLOB based storage.... ..."

"... In PAGE 17: ... Thus the time for this phase also increases with the number of processors. Table2 shows the speedup, efficiency and serial fraction measurements for this algorithm on KSR-1. We notice that the serial fraction increases with the number of processors.... ..."

"... In PAGE 17: ... Thus the time for this phase also increases with the number of processors. Table2 shows the speedup, efficiency and serial fraction measurements for this algorithm on KSR-1. We notice that the serial fraction increases with the number of processors.... ..."

"... In PAGE 6: ... Note that due to the reduced seed size, the advantages of going to a multiple polynomial technique increases. Table5 shows the experimental results together with comparisons with previous work. Figure 6: Serial Input Mode Compression Ratio (for ASIC 1) The table shows that a compression ratio of 33x can be achieved by using the new approach, whereas the conventional approach only resulted in 2x (or 9x with a serial shift mode).... ..."

"... In PAGE 20: ... Fig. 14 shows a serial of female models according to different parameters listed in Table1 . In Fig.... ..."