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Controlled and automatic human information processing
- I. Detection, search, and attention. Psychological Review
, 1977
"... A two-process theory of human information processing is proposed and applied to detection, search, and attention phenomena. Automatic processing is activa-tion of a learned sequence of elements in long-term memory that is initiated by appropriate inputs and then proceeds automatically—without subjec ..."
Abstract
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Cited by 874 (16 self)
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A two-process theory of human information processing is proposed and applied to detection, search, and attention phenomena. Automatic processing is activa-tion of a learned sequence of elements in long-term memory that is initiated by appropriate inputs and then proceeds automatically
MISD Compiler for Feature Vector Computation in Serial Input Images 1
"... In this paper a compiler capable of generate Multiple Instruction Single Data (MISD) architectures for feature vector calculation is presented. The input is a high-level language, avoiding to developers to involve in low level design. Instead, the output is expressed in a Hardware Description Langua ..."
Abstract
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Cited by 1 (1 self)
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In this paper a compiler capable of generate Multiple Instruction Single Data (MISD) architectures for feature vector calculation is presented. The input is a high-level language, avoiding to developers to involve in low level design. Instead, the output is expressed in a Hardware Description
Comparison of Two Switch And Three Switch Serial Input Interleaved Forward Converters
"... Abstract: This paper deals with comparison of two switch and three switch Interleaved Forward Converters. The DC input is converted into high frequency AC using Forward Converter. The AC is rectified using half-wave rectifier. The ripple in the output is filtered using LC filter. The peak to peak r ..."
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Abstract: This paper deals with comparison of two switch and three switch Interleaved Forward Converters. The DC input is converted into high frequency AC using Forward Converter. The AC is rectified using half-wave rectifier. The ripple in the output is filtered using LC filter. The peak to peak
Simulation and Implementation of the Two Switch Serial Input Interleaved Forward Converter
"... AbstractThe high voltage DC available in the telecommunication systems has to be converted into low voltage DC for batterycharging etc. This paper deals with simulation and implementation of two switch Interleaved Forward Converter for such application. The DC input is converted into high frequency ..."
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AbstractThe high voltage DC available in the telecommunication systems has to be converted into low voltage DC for batterycharging etc. This paper deals with simulation and implementation of two switch Interleaved Forward Converter for such application. The DC input is converted into high frequency
Evaluation Board for a 18-Bit Serial Input, Voltage Output DAC FEATURES
"... Full-featured evaluation board for the AD5781 ..."
Evaluation Board for a 20-Bit, Serial Input, Voltage Output DAC FEATURES
"... Full-featured evaluation board for the AD5791 ..."
Serial Input 16-Bit 4 mA–20 mA, 0 mA–20 mA DAC
"... 4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA current output 16-bit resolution and monotonicity ±0.012 % max integral nonlinearity ±0.05 % max offset (trimmable) ±0.15 % max total output error (trimmable) Flexible serial digital interface (3.3 MBPS) On-Chip loop fault detection On-chip 5 V reference (25 ppm/ ..."
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4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA current output 16-bit resolution and monotonicity ±0.012 % max integral nonlinearity ±0.05 % max offset (trimmable) ±0.15 % max total output error (trimmable) Flexible serial digital interface (3.3 MBPS) On-Chip loop fault detection On-chip 5 V reference (25 ppm
Memory for Serial Order: A Network Model of the Phonological Loop and its Timing
- Psychological Review
, 1999
"... A connectionist model of human short-term memory is presented that extends the 'phonological loop' (A.D. Baddeley, 1986) to encompass serial order and learning. Psychological and neuropsychological data motivate separate layers of lexical, timing and input and output phonemic information ..."
Abstract
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Cited by 176 (8 self)
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A connectionist model of human short-term memory is presented that extends the 'phonological loop' (A.D. Baddeley, 1986) to encompass serial order and learning. Psychological and neuropsychological data motivate separate layers of lexical, timing and input and output phonemic
■ Input
, 2008
"... The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA or DSB); either input ..."
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The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA or DSB); either input
Evaluation Board for a Quad-Channel, 16-Bit, Serial Input, 4 mA to 20 mA, Voltage Output DAC with Dynamic Power Control and HART Connectivity FEATURES Full-featured evaluation board for the AD5755, AD5755-1,
"... demonstration platform (SDP) PC software for control GENERAL DESCRIPTION The EVAL-AD575xSDZ is a full-featured evaluation board that is designed to allow the user to easily evaluate all features of the AD5755, AD5755-1, or AD5757, quad channel, 16-bit current source and voltage output DAC with dynam ..."
Abstract
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. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V. The part uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI,
Results 1 - 10
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1,250
