"... In PAGE 5: ... Table1 : Sequence of boot API calls over the life of a selected module (excluding the startup protocols). Steps 9.... ..."

"... In PAGE 4: ...The object faulting results compare the following alternative implementations of the read barrier: non-persistent: non-persistent Smalltalk, with the database entirely resident ID: tagged persistent identifiers FB: pointers to tagged resident proxies (fault blocks) trap: pointers to page-protected resident proxies In addition, the eagerness to swizzle is varied (where applicable): lazy: obtain a direct pointer only when traversing the reference (source locations are not updated) opportunistic: intra-segment references are swizzled when a segment of objects is made resident eager: all references to a target object are swizzled when the target is first made resident The results ( Table1 ) illustrate a clear tradeoff as the system warms up, with the up-front overheads of swizzling paying off only for warm and hot iterations. Hot performance reveals the payoff to be obtained through swizzling, with significantly reduced overheads (as highlighted by the number of instructions ex- ecuted per iteration), and performance very close to that of non-persistent.... ..."

"... In PAGE 3: ... 2 below illustrates activities involved in testing/integration, and the places where the activities take place. Table1 lists the most important TCS software modules and their actual development and testing status.... In PAGE 4: ... To be extended for VLT. NTT, Control model Optics Control Under development Adapter/Rotator Under development Module Status Tested on Table1... ..."

"... In PAGE 7: ... The serial PROM which stores the programmed mode bits will have to drive the ModeIn pin prior to the rising edge of the ModeClock, as per required data setup (TMDS) and hold time (TMDH). There are a total of 256 mode bits (see Table2 -1). The values of all the reserved bits must be set to a logic low or else the operation of the VR4000 is undefined.... In PAGE 8: ... The ModeClock signal will continue to toggle after reading in the mode bits until ColdReset* is reasserted. The bit# 63 of the mode bits allows the user to select the VR4000 to run with the PLL enabled or disabled (see Table2 -1). The normal operation of the processor with the PLL disabled is not supported and this mode is used for debugging of the silicon only.... In PAGE 8: ... The MasterOut and SyncOut will be stable when the ColdReset* is de-asserted; but the SClock, RClock amp; TClock will stablize 64 MasterClock cycles after the ColdReset* is de-asserted1. Although, it could be assumed that, regardless of which SysCkRatio (mode bits 15:17 in Table2 -1) the system interface is operating, the rising edge of PClock, SClock, RClock amp; TClock will be synchronized to the first rising edge of the MasterClock after the de- assertion of the ColdReset* signal. After the de-assertion of the ColdReset* signal, the Reset* signal needs to be asserted for at least 64 MasterClock cycles before the VR4000 is completely reset.... In PAGE 10: ...VR4000/VR4400 Reset and Initialization Sequence 2.2 Boot-Mode Settings Table2 -1 lists the processor boot-mode settings and the timing is shown in figure 2.1.... In PAGE 11: ...7 Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 9:10 SCBlkSz: Secondary cache line length, bit 10 most significant 0 4 words 1 8 words 2 16 words 3 32 words 11:14 XmitDatPat: System interface data rate, bit 14 most significant 0 D 1 DDx 2 DDxx 3 DxDx 4 DDxxx 5 DDxxxx 6 DxxDxx 7 DDxxxxxx 8 DxxxDxxx 9-15 Reserved 15:17 SysCkRatio: PClock to SClock divisor, frequency relationship between SClock, RClock, and TClock and PClock, bit 17 most significant 0 Divide by 2 1 Divide by 3 2 Divide by 4 3 Divide by 6 (R4400 processor only) 4 Divide by 8 (R4400 processor only) 5-7 Reserved 18 SIMasterMd: Master/Checker Mode (see mode bit 42); used in R4400 only.... In PAGE 12: ...VR4000/VR4400 Reset and Initialization Sequence Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 25:26 TWr2Dly: Secondary cache write assertion delay 2, TWr2Dly in PCycles, bit 26 most significant 0 1-3 Undefined Number of PClock cycles: Min 1, Max 3 27:28 TWr1Dly: Secondary cache write assertion delay 1, TWr1Dly in PCycles, bit 28 most significant 0 1-3 Undefined Number of PClock cycles; Min 1, Max 3 29 TWrRc: Secondary cache write recovery time, TWrRc in PCycles, either 0 or 1 cycle 0 1 0 cycle 1 cycle 30:32 TDis: Secondary cache disable time, TDis in PCycles, bit 32 most significant 0-1 2-7 Undefined Number of PClock cycles: Min 2, Max 7 33:36 TRd2Cyc: Secondary cache read cycle time 2, TRdCyc2 in PCycles, bit 36 most significant 0-2 3-15 Undefined Number of PClock cycles: Min 3, Max 15 37:40 TRd1Cyc: Secondary cache read cycle time 1, TRdCyc1 in PCycles, bit 40 most significant 0-3 4-15 Undefined Number of PClock cycles: Min 4, Max 15 41 0 Reserved 42 SCMasterMd: selects the type of Master/Checker mode (also see description of mode bit 18).... In PAGE 13: ...9 Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 46 Pkg179: R4000 Processor Package type 0 1 Large (447 pin) Small (179 pin) 47:49 CycDivisor: This mode determines the clock divisor for the reduced power mode.... In PAGE 14: ...VR4000/VR4400 Reset and Initialization Sequence Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 63 DsblPLL: Disables the phase-locked loops (PLLs) that match MasterClock and produce RClock, TClock, SClock, and the internal clocks.... In PAGE 25: ... The initialization of the mode bits, during the boot time, provides a great amount of flexibility to users in terms of processor configuration and operating parameters. These mode bits were described in chapter 2 ( Table2 -1). The initialization of caches and TLBs is done from the exception handler and the procedure was described via a pseudo code.... ..."

"... In PAGE 8: ...LIST OF TABLES Table1 : Key Dimensions of Prototype.... In PAGE 21: ...right in Figure 1 and Figure 2, are the back cavity section, the driver section, the area contraction section, the hot heat exchanger section, the stack section, the cold heat exchanger section, the area contraction section, and finally the resonator section. Key dimensions of the inside cross- section of the vessel are listed in Table1 . O-ring seals prevented leakage between each section.... ..."