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Results 11 - 20
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34
Public key cryptography empowered smart dust is affordable
"... Public key cryptography (PKC) has been considered for a long time to
be computationally too expensive for small battery powered devices. However, PKC
turned out to be very beneficial for issues such as key distribution, authentication etc.
In the recent years first research groups started to cope w ..."
Abstract
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Cited by 3 (1 self)
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required
for computation is negligible if the PKC is performed by power efficient hardware ac-
celerators. In such cases the corresponding transmission power becomes much more
significant. So we argue for dedicated hardware for elliptic curve cryptography in order
to reduce energy consumption
Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units
, 2012
"... With the advances of very large scale integration (VLSI) technology, the feature size has been shrinking steadily together with the increase in the design complexity of logic circuits. As a result, the efforts taken for designing, testing, and debugging digital systems have increased tremendously. A ..."
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. Although the electronic design automation (EDA) algorithms have been studied extensively to ac-celerate such processes, some computational intensive applications still take long execution times. This is especially the case for testing and validation. In order to meet the time-to-market constraints and also
Economics and Business-
"... Hardware accelerators in networking systems for control al-gorithms offer a promising approach to scale performance. To that end, several research efforts have been devoted to verify a hardware version of complex control algorithms but only for small-scale hardware unit tests. In this paper we propo ..."
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-posed framework a Belief-Propagation-driven algorithm ac-celerator for multicast packet scheduling. 1.
Loosely Coupled Accelerators for Reconfigurable SoC
"... Loosely coupled accelerators allow an intensive “pure software program ” (PSP) to share data seamlessly with ac-celerators. The method involves rewriting the source code, the hardware synthesis of the accelerated parts, and, of course, an architectural support. At algorithm design time, processing i ..."
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Loosely coupled accelerators allow an intensive “pure software program ” (PSP) to share data seamlessly with ac-celerators. The method involves rewriting the source code, the hardware synthesis of the accelerated parts, and, of course, an architectural support. At algorithm design time, processing
ORGFX- a Wishbone compatible Graphics Accelerator for the OpenRISC processor Per Lenander
, 2012
"... Modern embedded systems such as cellphones or medical instrumentation use increasingly complex graph-ical interfaces. Currently there are no widely used open hardware solutions to accelerate embedded graphical applications. This thesis presents the ORSoC graphics accelerator (ORGFX), an open hardwar ..."
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hardware graphics ac-celerator that can be used with programmable hardware. A standalone software implementation is provided to help for a quick development of accelerated applications. The accelerator is able to render 2D, 3D and vector graphics. The example implementation of the ORGFX is integrated
FPGA-based multigrid computations for molecular dynamics simulations
- In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (2007
"... Abstract: FPGA-based acceleration of molecular dynam-ics (MD) has been the subject of several recent studies. Implementing long-range forces, however, has only re-cently been addressed. Here we describe a solution based on the multigrid method. We show that multigrid is, in general, an excellent ma ..."
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Cited by 15 (10 self)
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match to FPGAs: the primary opera-tions take advantage of the large number of independently addressable RAMs and the efficiency with which complex systolic structures can be implemented. The multigrid ac-celerator has been integrated into our existing MD system, and an overall performance gain of 5x
A Scalable and Reconfigurable Shared-Memory Graphics Architecture
- In SIGGRAPH ’06: Material presented at the ACM SIGGRAPH 2006 conference
, 2006
"... Abstract: If the computational demands of an interactive gra-phics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accelerators may be utilised on multi-GPU based systems such as SLI [1] or Crossfire [2] or by a cluster of PCs in conjunctio ..."
Abstract
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Cited by 1 (0 self)
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in conjunction with a soft-ware infrastructure. Typically these PC cluster solutions allow the application programmer to use a standard OpenGL API. In this paper we describe an FPGA based hardware architecture, which provides an interface for multiple commodity graphics ac-celerators. Our scalable parallel
Phase I testbed description: Requirements and selection guidelines
, 1988
"... structed a reuse testbed for conducting software engineering experiments in soft-ware reusability. The hardware and system software of the testbed will provide a distributed computing environment with file-server capability for the storage of reusable components and other artifacts of the developmen ..."
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Cited by 1 (0 self)
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, and an environment. For each of these four testbed resources, the requirements are grouped into five areas: support of experiments, maximization of experience and reusability, applicability to problem domains, ac-celeration of technology transition, and advancing the state of the practice in reuse.
Architecting graphics processors for non-graphics compute acceleration
- In 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Special Session on Computer Architecture, Computer Graphics Proceedings, Annual Conference Series
, 2009
"... This paper discusses the emergence of graphics process-ing units (GPUs) that contain architecture features for ac-celerating non-graphics (or GPGPU) applications. It pro-vides an introduction for those interested in undertaking research at the intersection of manycore computing and GPU architecture. ..."
Abstract
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Cited by 1 (0 self)
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This paper discusses the emergence of graphics process-ing units (GPUs) that contain architecture features for ac-celerating non-graphics (or GPGPU) applications. It pro-vides an introduction for those interested in undertaking research at the intersection of manycore computing and GPU architecture
Crash fault detection in celerating environments
- In Intl. Par. and Distrib. Proc. Symp
, 2009
"... Failure detectors are a service that provides (ap-proximate) information about process crashes in a dis-tributed system. The well-known “eventually perfect” failure detector, 3P, has been implemented in partially synchronous systems with unknown upper bounds on message delay and relative process spe ..."
Abstract
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Cited by 4 (1 self)
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-plementations either use action clocks, which fail in ac-celerating environments, or use real-time clocks, which fail in decelerating environments. We propose the use of bichronal clocks, which are a composition of action clocks and real-time clocks. Our solution can be read-ily adopted to make existing
Results 11 - 20
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