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34
Reconfigurable hardware for high-security/ high-performance embedded systems: The safes perspective
- Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
, 2008
"... Abstract—Embedded systems present significant security chal-lenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedded systems on reconfigurable hardware and proposes a security architecture for embedded systems (SAFES). SAFES leverages ..."
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Cited by 8 (0 self)
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hierarchy of security controllers at the primitive, system and executive level. Results are presented for reconfigurable AES and RC6 security primitives and highlight the value of such an architecture. This paper also emphasizes that re-configurable hardware is not just a technology for hardware ac-celerators
Low-Cost Real-Time Gesture Recognition
- Proc. of 5th Asian Conference on Computer Vision
, 2002
"... A major impediment to developing real-time computer vision systems has been the computational power and level of skill required to process video streams in real-time. This has meant that many researchers have either analysed video streams off-line or used expensive dedicated hardware ac-celeration t ..."
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Cited by 2 (0 self)
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A major impediment to developing real-time computer vision systems has been the computational power and level of skill required to process video streams in real-time. This has meant that many researchers have either analysed video streams off-line or used expensive dedicated hardware ac-celeration
System-on-a-Chip (SoC) based Hardware Acceleration for Video Codec
- International Symposium on Photonics and Optoelectronics 2013, (to appear on Optics and Photonics Journal (OPJ
, 2013
"... Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically ..."
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Cited by 1 (1 self)
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dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware ac-celeration solution for video codec is proposed, which can also be used for other software applications. The characteris
ARCHITECTURE OF MPEG-7 COLOR STRUCTURE DESCRIPTION GENERATOR FOR REALTIME VIDEO APPLICATIONS
- INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (UP)
, 2004
"... Color structure descriptor (CSD) provides satisfactory image indexing and retrieval results amwg all color-based descriptors in MPEC-7. The superiority comes from the consideration of space distrihution of colors. Hardware accelerator is a must because its good performance is at the expense of high ..."
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computational com-plexity. In this paper, a design appronch of speci c hardware ac-celerators fnr dcscriptors is explored. The characteristics of CSD algorithm are also anzelyzed and an ef cient architecture is pro-posed. The proposed architecture can generate CSD description of 256 2 % image at SO frames per
Chapter 15 IPsec-Protected Transport of HDTV over IP∗
"... Abstract Bandwidth-intensive applications compete directly with the operating system’s network stack for CPU cycles. This is particularly true when the stack performs security protocols such as IPsec; the additional load of complex cryptographic transforms overwhelms modern CPUs when data rates exce ..."
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CPUs and networks. It appears to the application developer as a normal network interface, because the hardware ac-celeration is transparent to the user. The system is highly programmable and can support a variety of offload functions. A sample application is described, wherein production-quality HDTV
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
"... Abstract. The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems require efficient video coding algorithms and corresponding adaptive high-performance computational platforms ..."
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is to deliver a critical insight in the proposed solutions, and this way facilitate further research on accelerator architectures, architec-ture development methods and supporting EDA tools. The architectures are analyzed, classified and compared based on the core hardware ac-celeration concepts, algorithmic
unknown title
"... As operating systems progress to match faster hard-ware and higher user expectations, they seem to become less compatible with the needs of experimenters whose research requires real-time capabilities. Although some researchers have stated that this is a reason to continue utilizing nonmultitasking ..."
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environments (e.g., DOS; Myors, 1999), this strategy prevents the use of many advances, such as 32-bit graphic libraries and video hardware ac-celeration. Furthermore, although graphic libraries exist for DOS, most displays must be written directly to the video card (often in assembly language) to achieve
Barcelona Supercomputing Center
"... Abstract—As new heterogeneous systems and hardware ac-celerators appear, high performance computers can reach a higher level of computational power. Nevertheless, this does not come for free: the more heterogeneity the system presents, the more complex becomes the programming task in terms of resour ..."
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Abstract—As new heterogeneous systems and hardware ac-celerators appear, high performance computers can reach a higher level of computational power. Nevertheless, this does not come for free: the more heterogeneity the system presents, the more complex becomes the programming task in terms
Experimental Support for Reconfigurable Application-Specific Accelerators
- In Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), in conjuction with the International Symposium on Computer Architecture (ISCA
"... Abstract—New computer architectures are being proposed and will be implanted in the next few years. A common trend to improve the system performance is to include some reconfigurable logic components into future multi-core chips. Several prototypes already exist but there still is a lack of support ..."
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Cited by 2 (1 self)
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reconfigurable elements. the CPU, the inherent model is different from what hardware accelerators should expect. In this paper we present a new way of managing hardware ac-celerators. We propose a new programming and execution model for hardware accelerators based on the processing unit abstrac-tion. We study
Hardware Acceleration for Window Systems
- Computer Graphics
, 1989
"... Graphics pipelines are quickly evolving to support multi-tasking workstations. The driving force behind this evolution is the window system, which must provide high performance graphics within multiple windows, while maintaining inter-activity. The virtual graphics system presented by [7] provides a ..."
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Cited by 4 (0 self)
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aclean solution to the problem of context switching graphics hardware between processes, but does not solve all the problems associated with sharing graphics pipelines. The primary difficulty in context switching a graphics ac-celerator is the pipeline latency encountered uring a pipeline flush
Results 1 - 10
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