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Results 11 - 20
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2,044
Design of Efficient Hardware Utilization Fault Coverage Circuit
"... Abstract—A new fault coverage test pattern generator using a linear feedback shift register (LFSR) called FC-LFSR can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization. The g ..."
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Abstract—A new fault coverage test pattern generator using a linear feedback shift register (LFSR) called FC-LFSR can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
- IEEE VLSI Test Symp
, 2004
"... The path delay fault model is the most realistic model for delay faults. Testing all the paths in a circuit achieves 100 % delay fault coverage according to traditional path delay fault coverage metrics. These metrics result in unrealistically low fault coverage if only a subset of paths is tested, ..."
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Cited by 10 (1 self)
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The path delay fault model is the most realistic model for delay faults. Testing all the paths in a circuit achieves 100 % delay fault coverage according to traditional path delay fault coverage metrics. These metrics result in unrealistically low fault coverage if only a subset of paths is tested
Test Generation for CEFSM Combining Specification and Fault Coverage
- Coverage,” Proc. IFIP XIV Int’l Conf. Testing of Comm. Systems (TestCom 2002
, 2002
"... We discuss how specification coverage and fault coverage based test derivation strategies can be combined. In particular, the problem of deriving a test suffix, which raises tester confidence in the configuration of the system, reached after a test derived by a specification coverage criterion, i ..."
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Cited by 2 (2 self)
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We discuss how specification coverage and fault coverage based test derivation strategies can be combined. In particular, the problem of deriving a test suffix, which raises tester confidence in the configuration of the system, reached after a test derived by a specification coverage criterion
Fault coverage requirements in production testing of LSI circuits
- IEEE J. Sol. St. Circ
, 1982
"... A bstract–A technique is deseribed for evahsatingthe effectiveness of production tests for large wale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two pammeters, the average number (no) of faults on a faulty chip and the yield (Y ..."
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Cited by 21 (4 self)
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coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example. ~r HE reasons for the practical impossibility of obtaining a
Fault Coverage Estimation by Test Vector Sampling
, 1995
"... We develop a new statistical technique for estimating delay fault coverage in combinational circuits. True value simulation is performed for a sample of vector pairs chosen randomly from the test set. Transition probabilities and observabilities are estimated from the simulation data. These allow ..."
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Cited by 4 (2 self)
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We develop a new statistical technique for estimating delay fault coverage in combinational circuits. True value simulation is performed for a sample of vector pairs chosen randomly from the test set. Transition probabilities and observabilities are estimated from the simulation data
Upper Bounding Fault Coverage by Structural Analysis and
- Signal Monitoring,” in Proc. 24th IEEE VLSI Test Symp
"... A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, certain signal conditions are monitored during logic simulation. These signal conditions are specified by an analysis of do ..."
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Cited by 3 (2 self)
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data show a substantial reduction of error in statistical estimates obtained by a stuck-fault coverage estimator when corrected for faults found by this algorithm as guaranteed to be undetected by the given sequence. An effective application of this technique is demonstrated for scan-based test point
Fault Coverage Evaluation of Protocol Test Sequences
- Proc. of the 14th IFIP Symposium on Protocol Specification, Testing and Verification
, 1993
"... In this paper, we investigate the quality of a given protocol test sequence in detecting faulty implementations of the specification. The underlying model is a deterministic finite state machine (FSM). The basic idea is to construct all FSMs having n + i states (where n is the number of states in ..."
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Cited by 3 (0 self)
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and backjumping techniques are used to reduce the computational complexity. We have constructed a tool based on the model and used it in assessing several UIO-based optimization techniques. We observed that the use of multiple UIO sequences and overlaps can sometimes weaken the fault coverage of the test
Enhanced Fault Coverage Analysis Using ABVFI
"... Fault injection is an effective way to determine the fault coverage of an integrated circuit design and is usually ac-complished through simulation. Simulation is time inten-sive, making it impossible to simulate all possible input and fault combinations in a complex circuit under a re-alistic fault ..."
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Fault injection is an effective way to determine the fault coverage of an integrated circuit design and is usually ac-complished through simulation. Simulation is time inten-sive, making it impossible to simulate all possible input and fault combinations in a complex circuit under a re
Impact of Stresses on the Fault Coverage of Memory Tests
"... Memory tests are applied in the industry using different algorithmic stresses (e.g., data-backgrounds) and nonalgorithmic stresses (e.g., supply voltage). This paper presents an industrial analysis of the impact of stresses on the fault coverage (FC) of the memory tests. The experimental results sho ..."
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Memory tests are applied in the industry using different algorithmic stresses (e.g., data-backgrounds) and nonalgorithmic stresses (e.g., supply voltage). This paper presents an industrial analysis of the impact of stresses on the fault coverage (FC) of the memory tests. The experimental results
Statistical Methods for Delay Fault Coverage Analysis
- in Proc. of VLSI Design
, 1995
"... We develop new statistical techniques for delay fault analysis. True value simulation is performed using a multi-value logic system describing signal states of two consecutive vectors. Signal statistics are used to estimate transition probabilities and observabilities. These allow us to estimate det ..."
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Cited by 5 (1 self)
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detection probabilities and the coverage for transition faults. For path delay faults, recognizing that the total number of possible paths can be exponential in circuit size, we devise an implicit random path sampling procedure to obtain a linear-time estimate of the coverage for all faults. We further
Results 11 - 20
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2,044
