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Table 1: Parallel processors comparison

in Retinal Processing Emulation in a Programmable 2-Layer Analog Array Processor CMOS Chip
by R. Carmona, F. Jiménez-garrido, R. Domínguez-castro, S. Espejo, A. Rodríguez-vázquez
"... In PAGE 1: ... During the last years, di erent authors have focused on the realization of parallel preprocessing of multi-dimensional signals, using either purely digital techniques [1] or mixed-signal techniques, like in [2]. The data in Table1 can help us to compare these two approaches. Here, the peak computing power (expressed as operations per second: XPS) per unit area and power is shown.... In PAGE 2: ... Also, taking full advantage of the full digital resolution requires highly accurate A/D converters, what creates additional area and power overhead. The third row in Table1 corresponds to the chip presented here. This chip out- performs the one in [2] in terms of functionality as it implements a reduced model of the biological retina [3].... ..."

Table 2-2 contains a list of vector and parallel processors that are

in National Aeronautics and Space Administration
by Robert H. Sues, Heh-chyun Chen, Lawrence A. Twisdale, William R. Martin 1991

Table 3.4: Parallel processor performances of SMVM

in Acknowledgements
by unknown authors 2005

Table 4: AND Parallel Tests

in Implementing Prolog on Distributed Systems:
by Parallel Prolog Douglas, Douglas Eadline 1994
Cited by 3

Table 2.1: SIMD distributed-memory parallel processor implementations.

in A Study of the Functional Memory Type Parallel Processor
by Http Www Tamaru

Table 3: Summary of results with 5 processors and parallel heuristics

in Control Heuristics for Scheduling in a Parallel Blackboard System
by Keith Decker , Alan Garvey, Marty Humphrey, Victor Lesser 1993
"... In PAGE 15: ... Time: 5 processors with heuristics. Table3 is a comparison of the system with the 5 processors and the four heuristics with the 1 processor and 5 processor systems without the four heuris- tics. While 2.... ..."
Cited by 8

Table 3. Ideal and{parallelism Program Scheduling Processors

in IDRA (IDeal Resource Allocation): Computing Ideal Speedups in Parallel Logic Programming
by Fern'andez Carro Hermenegildo, M. J. Fern, Ez M. Carro M. Hermenegildo
"... In PAGE 7: ... Benchmarks with good performance in Tables 1 and 2 show good speedups here also. But the inverse is not true: benchmarks with low e ciency in max- imum parallelism can perform well in actual executions: for example the sim- ulated speedups for the benchmark bpebpf (Figure 3), are quite good for a reduced number of processors (see Table3 ). As expected, more regular bench-... ..."

Table II. Absolute Speedups for Parallelized Programs Number of Processors

in Symbolic bounds analysis of pointers, array indices, and accessed memory regions
by Radu Rugina, Martin C. Rinard 2000
Cited by 86

Table 3 Comparison of sequential and parallel (on four processors) execution times.

in D b D D Automatic
by unknown authors
"... In PAGE 18: ... Further experimentation is necessary to evaluate the accuracy of execution-time estimates for different programs. Table3 contains parallel-execution-time measurements for a small collection of programs from the GENESIS [58], PERFECT [59], and SPEC [60] benchmark sets. These programs are much larger than the example program discussed in Figures 1-5 and are more representative of real applications.... ..."

Table 6.4 Rotating geometry (parallel computation on 128 processors)

in A Multigrid Algorithm For The Mortar Finite Element Method
by Dietrich Braess, Wolfgang Dahmen, CHRISTIAN WIENERS 1999
Cited by 30
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