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Table 1. Number of cores in MPSoC applications

in Constraint-Driven Bus Matrix Synthesis for MPSoC
by Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane 2006
"... In PAGE 5: ... While VIPER and SIRIUS are variants of existing industrial strength applications, ORION4 and HNET8 are larger systems which have been derived from the next generation of MPSoC applications currently in development. Table1 shows the number of components in each of these applications. Note that the Masters column includes the processors in the design.... ..."
Cited by 5

Table 1. Number of cores in MPSoC applications

in Bus Matrix Communication Architecture Synthesis ∗
by Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane, Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane, Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane 2005
"... In PAGE 8: ... While VIPER and SIRIUS are variants of existing industrial strength applications, ORION4 and HNET8 are larger systems which have been derived from the next generation of MPSoC applications currently in development. Table1 shows the number of components in each of these applications. The Masters column includes the processors in the design, which are primarily ARM based microprocessors.... ..."

Table 1. Core distribution in MPSoC applications

in COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC
by unknown authors
"... In PAGE 5: ... PYTHON and SIRIUS are variants of existing industrial strength designs, VIPER2 and HNET8 are larger systems which have been derived from the next generation of MPSoC applications currently in development. Table1 shows the number of components in each of these applications, after HW/SW partitioning. Note that the Masters column includes the processors in the design, while the Slaves column does not include the memory blocks, which will be co-synthesized with the communication architecture later.... ..."

Table 1. Number of cores in MPSoC applications

in Bus Matrix Communication Architecture Synthesis ∗
by Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane, Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane, Sudeep Pasricha, Nikil Dutt, Mohamed Ben-romdhane 2005
"... In PAGE 8: ... While VIPER and SIRIUS are variants of existing industrial strength applications, ORION4 and HNET8 are larger systems which have been derived from the next generation of MPSoC applications currently in development. Table1 shows the number of components in each of these applications. The Masters column includes the processors in the design, which are primarily ARM based microprocessors.... ..."

Table 3: Timing Comparisons between our MPSoC emulation framework and MPARM

in 36.2 A Fast HW/SW FPGA-Based Thermal Emulation Framework for Multi-Processor System-on-Chip ABSTRACT
by David Atienza, Pablo G. Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose M. Mendias

Table III. Timing Comparisons between Our MPSoC Emulation Framework and MPARM

in HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs
by David Atienza, Pablo G. Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose M. Mendias, Roman Hermida

Table 1: Power for most important components of an MPSoC design (130nm bulk CMOS technology) Max. Power@100 MHz Max. Power density

in 36.2 A Fast HW/SW FPGA-Based Thermal Emulation Framework for Multi-Processor System-on-Chip ABSTRACT
by David Atienza, Pablo G. Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose M. Mendias
"... In PAGE 4: ... 5.1 Power estimation In Table1 , we summarize the values used for the components of our emulated MPSoC. These values have been derived from indus- trial power models for a 0.... In PAGE 6: ... The floorplan includes 28 thermal cells (Figure 4) and the dimensions of NoC components were ob- tained after building a layout. The dimensions and energy figures of memories and processors are shown in Table1 and were provided by an industrial partner. As SW driver, we have defined a workload of 100K matrices in the Matrix benchmark (MATRIX-TM in Table III and Figure 6) to stress the MPSoC processing power and observe thermal effects.... ..."

Table 1. Core distribution in MPSoC applications

in A Framework for Memory and Communication Architecture Co-synthesis In Mpsocs
by Sudeep Pasricha, Nikil Dutt
Cited by 1

Table 1: Snippet from an AIS for a generic MPSoC Operation Model

in Parallel and Distributed Systems Section
by A. L. Varbanescu
"... In PAGE 6: ... After identifying model resources, the AIS has to be specified as a set of rules for using these resources, requiring (1) in-depth knowledge on the functionality of the architecture, for detecting the resource accesses an instruction performs, and (2) resource latencies. As an example, Table1 presents a snippet from a (possible) AIS, considering an architecture with: several identical programmable processors (Procs(p)), each one having parallel arithmetic (ALU(p)) and multiplication (MUL(p)) units and its own L1(p) cache; several Specialized Functional Units (SFU(s)); a shared L2 cache, banked, with dedicated Refill and Victimize engines; virtually infinite off-chip memory (mem). Table 1: Snippet from an AIS for a generic MPSoC Operation Model... ..."

Table 1. Snippet from an AIS for a generic MPSoC Operation Model

in H.: PAM-SoC: A toolchain for predicting MPSoC performance
by Ana Lucia Varbanescu, Henk Sips, Arjan Van Gemund 2006
"... In PAGE 5: ... After identifying model resources, the AIS has to be specified as a set of rules for using these resources, requiring (1) in-depth knowledge on the functionality of the architecture, for detecting the resource accesses an instruction performs, and (2) resource latencies. As an example, Table1 presents a snippet from a (possible) AIS, considering an architecture with: several identical programmable processors (Procs(p)), each one having parallel arithmetic (ALU(p)) and multiplication (MUL(p)) units and its own L1(p) cache; several Specialized Functional Units (SFU(s)); a shared L2 cache, banked, with dedicated Refill and Victimize engines; virtually infinite off-chip memory (mem). Table 1.... ..."
Cited by 2
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