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Table 1. The difference between On-Chip Memory and cache

in SCIMA: A Novel Architecture for High Performance Computing
by Hiroshi Nakamura, Hideki Okawara, Taisuke Boku, Masaaki Kondo, Shuichi Sakai
"... In PAGE 2: ... Since the data set of HPC applications is large, off-chip DRAM is utilized as main memory. The main differences between On-Chip Memory and cache are shown in shown in Table1 . The location and the replacement of data are controlled by software ex- plicitly in On-Chip Memory, while those of cache are controlled by hardware implicitly.... ..."

Table 1: Comparison of link widths in off- and on-chip interconnects.

in unknown title
by unknown authors
"... In PAGE 2: ...1 Wiring In off-chip networks, wires are intra-board (using printed circuit boards), inter-board (through backplanes), and across cabinets (through cables). Links are not wide primarily because of pin-out limitations ( Table1 ). There is flexibility in the wiring layout arising from physical reality (3D space, many layer boards, multiple boards, relative freedom of wiring with backplanes and cabinets) and wire length is not a first order concern.... ..."

Table 5. Parasitic interconnect capacitance for on-chip 2D,3D and off-chip 2D for a 1024 bit bus

in PicoServer: Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor
by Taeho Kgil, Ali Saidi, Nathan Binkert, Ronald Dreslinski, Steven Reinhardt, Krisztian Flautner, Trevor Mudge 2006
"... In PAGE 6: ... We measured the toggle rate and access rate of these wires and calculated power using the well-known dynamic power equation to calculate interconnect power. Table5 shows the expected intercon- nect capacitance for 1024bits in the case of 2D on-chip, 3D stack- ing, and 2D off-chip implementations. Roughly speaking, on-chip implementations have at most 33% capacitance of an off-chip im- plementation.... ..."
Cited by 6

Table 1: Power consumption of SoC components @ 200 Mhz

in Power Analysis of System-Level On-Chip Communication Architectures
by Kanishka Lahiri , Anand Raghunathan
"... In PAGE 1: ... Very little work has addressed analyzing the nature of power consump- tion in the communication architecture as a whole. To highlight the need for studying communication architectures and their power requirements, we compare the power consumed by a typi- cal communication architecture to the power consumed by other system components in Table1 . The table presents data obtained from gate-level power measurements, and manufacturer data sheets, of several commer- cial SoC components, including a complete communication architecture (the AMBA on-chip bus [3]).... ..."

TABLE IV IO Transfer Rates of Benchmark Applications with 16 kB Instruction Cache, 16 kB data Cache, and 1 MB On-Chip DRAM on a 400 MHz Processor.

in Design Issues for High Performance Active Routers
by Tilman Wolf, Jonathan S. Turner

Table 2. Clock speed, on-chip and o -chip cache sizes, peak oating point and LIN- PACK performance of the processors.

in Scalable Parallel Sparse Factorization with Left-Right Looking Strategy on Shared Memory Multiprocessors
by Olaf Schenk, Klaus Gärtner, Wolfgang Fichtner
"... In PAGE 6: ... In this study we consider two di erent shared memory architectures: parallel vector supercomputers, a 12-CPU NEC SX-4 and a 16-CPU Cray J90, and two multiprocessor servers, an 8-CPU DEC AlphaServer 8400 and an 8-CPU SGI Origin 2000. Table2 summarizes the characteristics of the individual processors. Table 2.... In PAGE 8: ... The speedups are computed with respect to a very e cient serial implementation of the supernode left-looking algorithm. To calibrate our speedup gures with respect to the peak performance, we compare the oating point performance of our implementation on a single processor with the single processor performance of the LINPACK benchmark in Table2 . Although the solver is designed for matrices with a very sparse structure, it delivers 160 M op/s on the Cray J90 or 81 % of the LINPACK performance.... In PAGE 8: ... The irregularity of the grids leads to more complicated structures of the linear systems that must be solved during the simulation. The machines are shared memory multiprocessors and the processor characteristics are summarized in Table2 . We used an 32-processor SGI Origin 2000 with six- teen Gbytes of main memory, and an eight-processor DEC AlphaServer with two Gbytes of main memory.... ..."

Table 3. Combination of cache and On-Chip Memory

in SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing
by Masaaki Kondo Research, Masaaki Kondo, Hideki Okawara, Taisuke Boku 2000
"... In PAGE 5: ... Using the unification mechanism of section 2.4, three combinations of cache and On-Chip Memory in Table3 are evaluated. In the configuration (a), all the data is accessed through cache.... ..."
Cited by 3

Table 15: On-chip multiply details across systems B On-chip multiply details

in Automatically Tuned Linear Algebra Software
by R. Clint Whaley, Jack J. Dongarra 1998
"... In PAGE 31: ...Table 15: On-chip multiply details across systems B On-chip multiply details Table15 below shows details of the loop unrollings a blocking factors for the on-chip multiply on various systems. NB is the blocking factor, MU is the unrolling along the M loop, NU the unrolling along the N loop, and LAT is the latency factor.... ..."
Cited by 247

Table 15: On-chip multiply details across systems B On-chip multiply details

in Automatically Tuned Linear Algebra Software
by R. Clint Whaley, Jack Dongarra 1998
"... In PAGE 32: ...Table 15: On-chip multiply details across systems B On-chip multiply details Table15 below shows details of the loop unrollings a blocking factors for the on-chip multiply on various systems. NB is the blocking factor, MU is the unrolling along the M loop, NU the unrolling along the N loop, and LAT is the latency factor.... ..."
Cited by 247

Table 2 lists the total on-chip storage required for

in EM-Cube: An Architecture for Low-Cost Real-Time Volume Rendering
by Randy Osborne, Hanspeter Pfister, Hugh Lauer, Neil McKenzie, Sarah Gibson, Wally Hiatt, Hide Ohkami
"... In PAGE 10: ...9 36.9 Total 6296#2FC + 40 4723#2FC + 40 #23chips 6bytes#2Fpixel 3bytes#2Fpixel 4 1614 1221 8 827 630 16 433 335 32 237 187 Table2 : On-chip bu#0Ber storage for b =8#28Kbits#2Fchip where C is the number of chips#29 For lookup tables, we assume a two-tiered table opacity lookup with two 512byte tables and one 512 entry table per color component #283x512 bytes to- tal#29. Shading is not yet #0Cnalized.... ..."
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