Results 1 - 10 of 27

Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric

by Mohammad Javad Dousti, Massoud Pedram
"... Abstract — Quantum computers are exponentially faster than their classical counterparts in terms of solving some specific, but important problems. The biggest challenge in realizing a quantum computing system is the environmental noise. One way to decrease the effect of noise (and hence, reduce the ..."
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technology. This algorithm, and the accompanying software tool, advances state-of-the-art in quantum CAD methodologies and methods while considering key characteristics and constraints of the ion-trap quantum circuit fabric. Experimental results show that the presented tool improves results of the previous

Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

by Naser Mohammadzadeh , Tayebeh Bahreini , Hossein Badri
"... Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in o ..."
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Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology

LEQA: Latency Estimation for a Quantum Algorithm Mapped to a Quantum Circuit Fabric

by Mohammad Javad Dousti , Massoud Pedram - in DAC , 2013
"... ABSTRACT This paper presents LEQA, a fast latency estimation tool for evaluating the performance of a quantum algorithm mapped to a quantum fabric. The actual quantum algorithm latency can be computed by performing detailed scheduling, placement and routing of the quantum instructions and qubits in ..."
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ABSTRACT This paper presents LEQA, a fast latency estimation tool for evaluating the performance of a quantum algorithm mapped to a quantum fabric. The actual quantum algorithm latency can be computed by performing detailed scheduling, placement and routing of the quantum instructions and qubits

Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits

by A. Shafaei, Bejestan M. Pedram, M. J. Dousti
"... Abstract This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can, on average, perform any logical fault-tolerant (FT) quantum operations with the min-imum latency. The operation scheduling, placement, and qubit routing proble ..."
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Abstract This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can, on average, perform any logical fault-tolerant (FT) quantum operations with the min-imum latency. The operation scheduling, placement, and qubit routing

Superconducting circuits Superconducting Circuits for Quantum Information: An Outlook

by M H Devoret , R J Schoelkopf
"... The performance of superconducting qubits has improved by several orders of magnitude in the past decade. These circuits benefit from the robustness of superconductivity and the Josephson effect, and at present they have not encountered any fundamental physical limits. However, building an error-co ..."
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principles that would prohibit the building of quite large quantum processors. The demonstrated capabilities of superconducting circuits, as in trapped ions and cold atoms, mean that QIP is beginning what may be one of its most interesting phases of development. Here, one enters a true terra incognita

Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

by Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
"... Abstract — Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid ..."
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Abstract — Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid

IEEE 2009 Custom Intergrated Circuits Conference (CICC) A 0.92mm 2 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application

by Shao-wei Yen, Ming-chih Hu, Chih-lung Chen, Hsie-chia Chang, Shyh-jye Jou, Chen-yi Lee
"... Abstract—An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware comp ..."
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complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a divisionfree reconfigurable interleaver architecture is implemented by simple addition and subtraction instead

Fabrication of a 34 × 34 Crossbar Structure at 50 nm Half-pitch by UV-based Nanoimprint Lithography

by Y. Chen, William M. Tong, R. Stanley Williams , 2004
"... We have developed a single-layer UV-nanoimprint process, which was utilized to fabricate 34 × 34 crossbar circuits with a half-pitch of 50 nm (equivalent to a bit density of 10 Gbit/cm2). This process contains two innovative ideas to overcome challenges in the nanoimprint at shrinking dimensions. Fi ..."
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. First, our new liquid resist formulation allowed us to minimize the residual resist layer thickness after curing and requires the relatively low imprint pressure of 20 psi. Second, by engineering the surface energy of the substrate we also eliminated the problem of trapped air during contact

A Threshold Logic Full Adder Based on Resonant Tunneling Transistors

by Christian Pacha, Karl Goser, Andreas Brennemann, Werner Prost, Universität Dortmund, Gerhard-mercator-universität Duisburg - In Proceedings of the 24th European SolidState Circuits Conference ESSCIRC , 1998
"... Resonant tunneling transistors and circuit architectures with enhanced computational functionality are promising candidates for future nano-scale integration. In this paper we propose a full adder cell based on multiple terminal linear threshold gates. The threshold gates are composed of monolithica ..."
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of monolithically integrated resonant tunneling diodes and heterostructure field effect transistors. Together with a bit-level pipelining scheme this leads to an efficient implementation with a minimal logic depth of two circuit layers. 1 Introduction During the last decades the progress in microelectronics

Physics

by Daniel Alexander Pertot, Jacobus Verbaarschot, Two-component Bosons In, Daniel Alexander Pertot , 2011
"... Ultracold atoms in optical lattices provide a highly control-lable environment for the clean experimental realization of various model Hamiltonians from condensed matter and statistical physics. For example, the two-component Bose-Hubbard model, which re-duces to an anisotropic spin-1/2 Heisenberg m ..."
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model in a certain limit and thus allows for the study of quantum magnetism, can be im-plemented by using bosons with two different internal states that couple differently to an optical lattice potential. In this thesis, I present our first experiments with two-component hyperfine-state mixtures
Results 1 - 10 of 27