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Table 18: SoC Area

in Dynamic Memory Management for Embedded Real-Time Multiprocessor System on a Chip
by Mohamed A. Shalan 2003
"... In PAGE 111: ... Table18 shows the sizes of the di erent SoC components expressed in number of transistors. The four ARM9TDMI cores consume 448K transistors [33].... ..."
Cited by 2

Table 2 Target SoC overview.

in
by unknown authors
"... In PAGE 3: ... Implementation We developed an FPGA-based real-time system prototyping tool and used it for SoC development for a leading-edge digital consumer product. Table2 shows an overview of the target SoC. It consists of an IBM PowerPC* processor, image processing units, and various input/output (I/O) peripherals.... ..."

Table 3 Faulty SoC scenarios

in unknown title
by unknown authors 2006
"... In PAGE 14: ... The estimation of the ability in time reduction for diagnosis was worked out considering four significant fault sets including typical defects. Table3 summarizes the investigat- ed faulty SoC scenarios; details about fault models are given for the faulty cores. The diagnosis time for each scenario is shown when adopting our approach, and compared with a classical ATE-based diagnosis solution: in the latter case, the diagnosis process is done separately for each core identified as faulty.... ..."

Table 1: Power consumption of SoC components @ 200 Mhz

in Power Analysis of System-Level On-Chip Communication Architectures
by Kanishka Lahiri , Anand Raghunathan
"... In PAGE 1: ... Very little work has addressed analyzing the nature of power consump- tion in the communication architecture as a whole. To highlight the need for studying communication architectures and their power requirements, we compare the power consumed by a typi- cal communication architecture to the power consumed by other system components in Table1 . The table presents data obtained from gate-level power measurements, and manufacturer data sheets, of several commer- cial SoC components, including a complete communication architecture (the AMBA on-chip bus [3]).... ..."

Table 1 The SoC cores test strategies, coverage, test frequency, power consumption (w.r.t. maximum allowed chip dissipation power) and test application time

in unknown title
by unknown authors 2006
"... In PAGE 12: ...Memory core 5 is equipped with programmable BIST circuitry [10] and programmed to apply a March FT (whose complexity is 2F+2N*P+6N*R, where R, P and F represent the number of read, program and flash operations, respectively, and N is the number of words); amp; Memory core 6 is equipped with programmable BIST circuitry [1] and programmed to apply a 10N March C-algorithm. Table1 summarizes properties of the cores, including the power consumption (percentage with respect to maximum allowed circuit dissipation power) and test time corresponding to the execution of the selected test strategies at the core nominal frequency. The I-IP and Diagnosis-oriented TAM were described in VHDL language resorting to about 4,000 code lines and adapted to the case study: amp; The I-IP manages three groups, one including four cores, the others including three cores each amp; The instruction size is 16 bits and the Code buffer is intended to be a ROM memory (142 bytes) amp; The Result buffer is a RAM memory (1 Kbyte).... ..."

Table 1: Results of time-cost tradeoff for the running SoC example.

in An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
by Mehrdad Nourani, Christos Papachristou 2000
"... In PAGE 7: ... A C program translates the SoC specification to BAG, applies the DFS algo- rithm and generates the constraints in lp solve format in a few seconds. The results of the running SoC exam- ple (see Figure 3) is shown in Table1 for three choices of (Wt; Wc). For the first choice (1; 0), the ILP formu- lation finds the fastest access schedule (3 time steps) with no consideration of cost.... ..."
Cited by 25

Table 1: Silicon area for original and BDL versions. %DfD %SoC

in Analysis and Design Aids General Terms Design
by Bart Vermeulen, Mohammad Z. Urfianto, Sandeep K. Goel
"... In PAGE 4: ... We are investigating a resource optimization step in the compiler to automatically detect the possibility to use a single detector for multiple events, thereby reducing the required area. Regardless of the resource optimization step, to properly appreciate the area numbers reported in Table 1, we need to consider the total area of the SoCs these break- point modules are used in, as is shown in the fth column of Table1 . For all cases, the actual breakpoint module itself occupied far less than 0.... ..."

Table 3. Feature comparison of design alternatives for a processor/FPGA based SoC

in Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
by H. Blume, H. Hübert, H. T. Feldkämper, T. G. Noll 2002
"... In PAGE 11: ...ore flexible than the pure HW-FPGA implementation. E. g., a change in and a verification of the rule based blocks takes about an hour for the SW implementation in the processor core whereas a change in the pure HW-FPGA implementation takes several hours. In Table3 the specific parameters of the two alternatives for a 256x256 pixel image are compared. Table 3.... ..."
Cited by 6

Table IV. Results for a 2-processing-element SoC / no cache coherency.

in Cluster-based Partial-order Reduction
by Twan Basten , Marc Geilen, et al. 2004
Cited by 1

Table 1: Simulation speed results for the case study SoC design.

in A Generic Framework for Rapid Prototyping of System-on-Chip
by Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich, Alexey Kupriyanov
"... In PAGE 6: ... This is very convenient during step- by-step architecture debugging. With the help of sev- eral optimization techniques based on graph theoretic approaches [19], a speedup of 6 was achieved compared to Modelsim, see Table1 . Because of the asynchronous communication mode the high potential of these tech- niques for synchronous designs [19], [20] could not be fully exploited in this case.... ..."
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