"... In PAGE 26: ... However, some timing failures that are embedded in short paths may not cause delay faults at normal operating conditions. Table3 -1 lists the causes of timing failures and the possible testing techniques for detecting them. Although all of these failures may be detected by delay fault testing, the success of detection depends on the significance of the excessive delay in the defective circuit.... In PAGE 27: ...3.1 Causes and Failure Modes of Timing Failures Table3 -1 lists the causes of timing failures. Transmission gate opens occur when one of the transistors in a CMOS transmission gate is malfunctioning and cannot pass any signals.... In PAGE 28: ... Tunneling opens allow CUTs to be functional at low frequencies but cause failures at higher frequencies [Henderson 91]. Table3 -2 summarizes the failure modes of the timing failures described above. This chapter discusses how VLV testing can improve the detectability of timing failures that are caused by degraded signals and by transistors with lowered driving capabilities.... In PAGE 29: ... Table3 -2 Failure Modes of Timing Failures Causes Failure Modes Transmission gate opens Degraded signals Threshold voltage shifts Increased gate delays Slow-to-fall signals Diminished-drive gates Increased gate delays Slow-to-rise signals Slow-to-fall signals Gate oxide shorts Degraded signals Increased leakage Metal shorts Degraded signals Increased leakage Defective interconnect buffers Degraded signals Increased gate delays Increased RC delays Increased leakage Opens High resistance interconnects, via defects Increased RC delays Slow-to-rise signals Slow-to-fall signals Tunneling opens CUT fails at high frequencies 3.2 Voltage Dependence of CMOS Propagation Delay VLV testing is most effective in detecting delay flaws when the supply voltage is around the value where the propagation delay of a circuit starts to change significantly as the supply voltage is reduced.... In PAGE 31: ...5Vt, which is the same as the voltage range for VLV testing proposed in Chapter 2. Table3 -3 lists the delay ratios of WD and fault-free gates at different voltages for... In PAGE 32: ....6 m m technology can be found in Appendix B. As shown in Appendix B, we also used more complicated circuits to verify the conclusion. Figure 3-2 Voltage Dependence of the Change Rate of the Propagation Delay of a CMOS Inverter Table3 -3 WD Delay Ratios for the 0.8 m m Technology Vdd Vdd / Vtn Td(Vdd )* a TWD(Vdd)** Delay Ratio TWD(Vdd)/ Td(Vdd) 1.... In PAGE 35: ...nd the 0.6 m m technology are similar, only the results for the 0.6 m m technology are discussed in this dissertation. Table3 -4 shows the simulation results for the 0.6 m m technology.... In PAGE 36: ... Table3 -4 Delay Ratio between Faulty and Fault-Free High-Drive Gate in Fig. 3-3 for the 0.... ..."

"... In PAGE 2: ... A virtualized system cannot deliver performance beyond what the physical hardware is capable of providing after subtracting the overhead required to manage the virtualization. Table1 contains a list of major components that may be either virtual or physical. The capacity or capability of each physical component may be specified by the hardware manufacturer or measured by some accepted methodology.... In PAGE 2: ... Studies have shown that the measurements taken at the logical component level may differ significantly from corresponding measurements at the Virtualization Manager level [BD]. In this paper, we assume that all measurements for the performance metrics defined in Table1 are collected at the Virtualization Manager level. Suppose a virtualized system has n partitions or guests, n G G G , , , 2 1 L , running on a physical system whose four hardware components are Processor P, Memory M, I/O subsystem D, and Network N.... ..."

"... In PAGE 20: ... However, as numerical experiments will show, we lose accuracy compared with the projection and SAT method because of the incorrect boundary treatment. Table5 and 6 show the grid re nement study for the projection method (25) and the SAT method (27). The error is chosen such that the error of the time discretization is smaller than the error of the space discretization and such that the condition (18) holds.... ..."

"... In PAGE 9: ... Further, at most one layer of hidden units was used, and no coupled weights were used there. Table4 gives some of the results we obtained with time-delay networks. The most obvious feature of this table is how well the combination of categories 4, 5, and 6 again appears to work with this network architecture.... ..."