### Table 2: Some combinational circuits with large number of

"... In PAGE 5: ... As long as the initial decision diagram are successfully created, the XORDD-based method can always generate results. Table2 listed several circuits for which a b b d 1 1 1 c c c c 1 1 1 c c c c c 1 a b b d 1 0 1 0 0 01 1 0 1 1 0 010 c d 1 11 a b bc 1 1 0 00 1 0 01 01 b c a b c d 1 1 1 b d 1 10 0 0 11 a b b c c d c 1 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 c 1 1 a b b c d 1 0 0 0 1 1 00 1 0 01 010 1 0 1 0101 01 1 0 0 (b) (c) (e) (f) (a) (d) =aba c cd Figure 7: An example showing how the algorithm is per- formed on a function|-from initial BDD to the #0Cnal com- pact XORDD, which gives a minimized ESOP form ESPRESSO did not produce any result in 30 minutes on a SUN SPARCworkstation. The last column node in Table 2 represents the number of nodes in an XORDD.... ..."

### Table 5: Experimental Circuits

2005

"... In PAGE 7: ... These circuits are synthesized into LUTs using the EMC datapath-oriented synthesis process as described in [22], which preserves the regularity of datapath circuits while attempting to minimize area. Table5 gives the name, size (number of BLEs) of each circuit for each synthesis granularity value (here the synthesis granularity is defined to be the maximum datapath width that is preserved by the synthesis process and is an input to the synthesis). The synthesized circuits are then packed into multi-bit logic blocks using the CNG datapath-oriented packing algorithm as described in [23].... ..."

Cited by 6

### Table 2. Circuit statistics.

2001

"... In PAGE 5: ... In either case, added CPU time and processing time was less than 10% of sequential TGT. Table2 shows statistics for ISCAS 89 benchmark circuits and their BCC. Three columns under FFs, namely Total, Scan and Scan(%), give the total number of FFs, number of scan FFs used to make the circuit acyclic and % of scan FFs, re- spectively.... In PAGE 5: ... The test gen- eration time for such multiple-mapped fault is same as any other single fault. The last column in Table2 shows the % of multiple-mapped faults (MF) that had to be modeled. We found that most (about 95%) of the undetected faults did not require multiple fault mapping.... ..."

Cited by 5

### Table 2. Circuit statistics.

"... In PAGE 5: ... In either case, added CPU time and processing time was less than 10% of sequential TGT. Table2 shows statistics for ISCAS 89 benchmark circuits and their BCC. Three columns under FFs, namely Total, Scan and Scan(%), give the total number of FFs, number of scan FFs used to make the circuit acyclic and % of scan FFs, re- spectively.... In PAGE 5: ... The test gen- eration time for such multiple-mapped fault is same as any other single fault. The last column in Table2 shows the % of multiple-mapped faults (MF) that had to be modeled. We found that most (about 95%) of the undetected faults did not require multiple fault mapping.... ..."

### Table 4: Mapping Capability Results on Benchmark Circuits

"... In PAGE 4: ... Both LUTs include one extra bit for the mode selection. The experimental results are shown in Table4 . The ta- ble shows the number of 4-1 LUTs, the number of real 4 in- put functions, the number of our 3-1 LUTs computed using the mapping algorithm, the number of functions mapped to two 3-1 LUTs, the number of 3-1 LUTs normalized with 0.... ..."

### Table 3: CLBs required for mapping the circuits

### Table 1. Power Consumption Reduction Results for Parity Checkers for some Combinational Circuits when the minimal.genlib library is used

2002

"... In PAGE 7: ...imulation method). Separate runs using the minimal.genlib and mcnc.genlib technology libraries were performed, since the optimal permutation obtained, as well as the reduction in power consumption achieved, varies according to the library used for technology mapping. Table1 presents the results for parity checkers for some combinational benchmark circuits chosen from the LGSynth91 suite, mapped using the minimal.genlib technology library.... ..."

Cited by 8

### Table 1. Power Consumption Reduction Results for Parity Checkers for some Combinational Circuits when the minimal.genlib library is used

2002

"... In PAGE 7: ...imulation method). Separate runs using the minimal.genlib and mcnc.genlib technology libraries were performed, since the optimal permutation obtained, as well as the reduction in power consumption achieved, varies according to the library used for technology mapping. Table1 presents the results for parity checkers for some combinational benchmark circuits chosen from the LGSynth91 suite, mapped using the minimal.genlib technology library.... ..."

Cited by 8

### Table 1. Power Consumption Reduction Results for Parity Checkers for some Combinational Circuits when the minimal.genlib library is used

2002

"... In PAGE 7: ...imulation method). Separate runs using the minimal.genlib and mcnc.genlib technology libraries were performed, since the optimal permutation obtained, as well as the reduction in power consumption achieved, varies according to the library used for technology mapping. Table1 presents the results for parity checkers for some combinational benchmark circuits chosen from the LGSynth91 suite, mapped using the minimal.genlib technology library.... ..."

Cited by 8

### Table 1. Comparison of Area and Energy/bit requirements of circuits

"... In PAGE 9: ... Fi- nally, throughout the capture range the power consumption is pretty much independent on the input . Table1 shows the average energy per bit requirements obtained during simulation of the devices. The test-bench 0 5 10 15 20 0 2 4 6 8 10 Output Time Separation/Latency (FO4) Input Time Separation (FO4) Response of TSE design Fall Rise Latency (fall) Latency (rise) (a) Gate-level design 0 5 10 15 20 0 2 4 6 8 10 Output Time Separation/Latency (FO4) Input Time Separation (FO4) Response of TSE design (transistor level) Fall Rise Latency (fall) Latency (rise) (b) Transistor-level design Figure 19.... ..."