NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods (2004)

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by Vishak Venkatraman , Andrew Laffely , Jinwook Jang , Hempraveen Kukkamalla , Zhi Zhu , Wayne Burleson

Venue:	Proc. SLIP 2004
Citations:	4 - 0 self

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Datum	Value	Source
TITLE	NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods	INFERENCE
AUTHOR NAME	Vishak Venkatraman	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Electrical and Computer Engineering; University of Massachusetts	SVM HeaderParse 0.2
AUTHOR ADDR	Massachusetts, USA	SVM HeaderParse 0.2
AUTHOR NAME	Andrew Laffely	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Electrical and Computer Engineering; University of Massachusetts	SVM HeaderParse 0.2
AUTHOR ADDR	Massachusetts, USA	SVM HeaderParse 0.2
AUTHOR NAME	Jinwook Jang	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Electrical and Computer Engineering; University of Massachusetts	SVM HeaderParse 0.2
AUTHOR ADDR	Massachusetts, USA	SVM HeaderParse 0.2
AUTHOR NAME	Hempraveen Kukkamalla	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Electrical and Computer Engineering; University of Massachusetts	SVM HeaderParse 0.2
AUTHOR ADDR	Massachusetts, USA	SVM HeaderParse 0.2
AUTHOR NAME	Zhi Zhu	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Electrical and Computer Engineering; University of Massachusetts	SVM HeaderParse 0.2
AUTHOR ADDR	Massachusetts, USA	SVM HeaderParse 0.2
AUTHOR NAME	Wayne Burleson	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Electrical and Computer Engineering; University of Massachusetts	SVM HeaderParse 0.2
AUTHOR ADDR	Massachusetts, USA	SVM HeaderParse 0.2
ABSTRACT	Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC) structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer interconnect issues to plan and quantify achievable performance. In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect Calculator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs involved to achieve better a priori interconnect planning. NoCIC determines the interconnect performance and power based on select NoC and circuit parameters. The effects of each parameter on the interconnect performance and power are expressed through various two-dimensional and three-dimensional plots.	SVM HeaderParse 0.2
YEAR	2004	INFERENCE
VENUE	Proc. SLIP 2004	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	69--75	INFERENCE
CITATIONS	18 found	ParsCit 1.0