Generation of yield-aware pareto surfaces for hierarchical circuit design space exploration

Generation of yield-aware pareto surfaces for hierarchical circuit design space exploration (2006)

by Saurabh K Tiwary

Venue:	In DAC
Citations:	8 - 0 self

Datum	Value	Source
TITLE	Generation of yield-aware pareto surfaces for hierarchical circuit design space exploration	INFERENCE
AUTHOR NAME	Saurabh K Tiwary	SVM HeaderParse 0.2
AUTHOR AFFIL	; Carnegie Mellon University; Pittsburgh,PA USA; Categories and Subject Descriptors	SVM HeaderParse 0.2
ABSTRACT	Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.	SVM HeaderParse 0.2
YEAR	2006	INFERENCE
VENUE	In DAC	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	31--36	INFERENCE
CITATIONS	19 found	ParsCit 1.0