Multiple process execution in cache related preemption delay analysis

Multiple process execution in cache related preemption delay analysis (2004)

by Jan Staschulat , Rolf Ernst

Venue:	In ACM International Conference on Embedded Software
Citations:	13 - 0 self

Datum	Value	Source
TITLE	Multiple process execution in cache related preemption delay analysis	INFERENCE
AUTHOR NAME	Jan Staschulat	SVM HeaderParse 0.2
AUTHOR AFFIL	Technical University of Braunschweig; Institute of Computer and Communication Network Engineering	SVM HeaderParse 0.2
AUTHOR ADDR	D-38106 Braunschweig, Germany	SVM HeaderParse 0.2
AUTHOR NAME	Rolf Ernst	SVM HeaderParse 0.2
AUTHOR AFFIL	Technical University of Braunschweig; Institute of Computer and Communication Network Engineering	SVM HeaderParse 0.2
AUTHOR ADDR	D-38106 Braunschweig, Germany	SVM HeaderParse 0.2
ABSTRACT	Cache prediction for preemptive scheduling is an open issue despite its practical importance. First analysis approaches use simplified models for cache behavior or they assume simplified preemption and execution scenarios that seriously impact analysis precision. We present an analysis approach which considers multiple executions of processes and preemption scenarios for static priority periodic scheduling. The results of our experiments show that caches introduce a strong and complex timing dependency between process executions that are not appropriately captured in the simplified models.	SVM HeaderParse 0.2
YEAR	2004	INFERENCE
VENUE	In ACM International Conference on Embedded Software	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
CITATIONS	27 found	ParsCit 1.0